Hi Team,
We see the following applications in the Alder Lake/Amston Lake reference schematic.
TPS7A85A:
1.2V to 0.9V/ I=3A
1.2V to 0.9V/ I=3.9A
I'm worried that there will be a dropout issue, so please help confirm if such an application will have an issue.
Thank you
Hi Kuo,
Is this a TI reference design, if so can you link to it?
For the TPS7A85A:
If Vin is below 1.4V, then there must be a BIAS rail or else the UVLO will not trip. The typical characteristics have the dropout with a BIAS rail at less than 200mV and the worst case dropout is 240mV; thus your operating conditions should be fine.
For the TPS7A57:
If you do not have a BIAS rail then you can switch to the TPS7A57. This LDO exceeds the performance of the TPS7A85A. The TPS7A57 is a 5A device and does not require an external BIAS rail to operate down to Vin = 1.1V using the internal charge pump. The TPS7A57 is an ultra high PSRR and low noise LDO with state of the art transient performance, in case those performance characteristics are of interest to you. The dropout is about half of the TPS7A85A even at higher current loading.
Thanks,
Stephen
