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LMG3410R070: Data sheet grounding clarification

Part Number: LMG3410R070

Questions relate to information given about the LMG3410R070 requirements relating to the ground planes and source connection regarding termination of bypass capacitors and the boost inductor. From data sheet - SNOSD10F –APRIL 2016–REVISED MAY 2020

 

 Terms used are "Signal ground", ground, SOURCE plane and SOURCE pin.

 Their use is not clear in the data sheet as it appears there are conflicts with the lay-out example shown in the data sheet. Figure 19.

“ 11.1.2 Signal Ground Connection (page 24)

The LMG341xR070's SOURCE pin is also signal ground reference. The signal GND plane should be connected to SOURCE with low impedance kelvin connection. In addition, the return path for the passives associated to the driver (e.g. bypass capacitance) must be connected to the GND plane. In Figure 19, local signal GND planes are located on the second copper layer to act as the return for the local circuitry. The local signal GND planes are isolated from the high-current SOURCE plane except the kelvin connection at the source pin through enough low impedance vias.”

 

Question 1

 Please clarify, is "signal GND plane" the same as "GND plane". In the lay-out example given in the data sheet there is confusion as C8 -Figure 14 Schematic Page 17 and  C8 -Figure 19 Example Half-Bridge Layout appears to be connected to "signal GND plane by two vias and directly to Q1 (Top GaN) Source. This appears to conflict with Kelvin connection as the "signal GND" is connected to "Q1- source in two places.

 

Other Clauses using these terms

 

11.1.3 Bypass Capacitors (page 24) - what does ground plane refer to in this instance.

 

9.2.2.3 Buck-Boost Converter Design ( page 19)  - Data sheet says "... This inductor is connected between the BBSW pin and ground. A 2.2 μF, 25V 0805 bypass capacitor is required between VNEG and ground. ..."

 

Question 2

2.2u capacitor is connected to Source ground. Inductor is connected to the signal GND in Figure 19 Example Half-Bridge Layout? – Why, would this not inject peak currents into signal ground?

Could you please clarify the terminology used in the data sheet. 

 Terms used are "Signal ground", ground, SOURCE plane and SOURCE pin.

Thanks,

Ed

            

  • Hi Ed,

    The source of each device is the ground for that device. For the low side device in a half bridge, this is easy because source connects to the system ground. For the high side device this is a little more confusing, the source is connected to the switch node so the ground for the high side device (and integrated driver) is the switch node. For the integrated driver and features we offer with it we suggest decoupling caps (and on our D-mode devices require an inductor) which will be connected to the device's ground/source pin. We suggest to make this signal ground to source ground connection through a kelvin connection by making the Vias away from the path that will conduct the power current. A good example of this is in the EVM we have, I have included the link for the design files for this EVM here: https://www.ti.com/lit/zip/snoc043

    Best,

    Kyle Wolf

  • Hi Kyle,

    Absolutely understand the term "ground" referring to the top or bottom GaN and the Kelvin connection from signal ground to Vs ground.

    The Gerbers you sent were helpful and clear.

    I would suggest the schematic could be clearer using a symbol for the Kelvin connection to split the signal ground and Vs ground, then it is easy to indicate the individual component grounding requirements directly on the schematic.
    eg “Net Tie” in Altium for Kelvin connection.

    I'm guessing the buck-boost inductor grounding is on the control ground rather than Vs ground due to low side current sensing control of the hysteric regulator?

    Thanks very much for your help and swift response,

    Ed

  • Hi Ed,

    Yes, the ground for the buck-boost inductor is on the control ground side of the kelvin connection.

    Best,

    Kyle Wolf

  • Thanks - Kyle - Ed