We have a design which has SM/PMBus pulled-up later than the power sequence of TPS546C20A through CNTL pin.
- This results in “oth” flagged in STATUS_CML (7Eh) register, subsequently pulling-down SMB_ALRT.
- By sending command CLEAR_FAULTS (03h), SMB_ALRT is cleared.
- This has been tested on TPS546C20AEVM1-746 evaluation module:
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Is this an expected behaviour, and will SMB_ALRT being pulled low affect power supply output?
If PMBus is not implemented and TPS546C20A operates fully pin-strapped, is there any adverse effect if DATA, CLK and ALERT remains connected to the SMBus?