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BQ76952EVM: FET Status bit : ALRT_PIN, DDSG_PIN, DCHG_PIN asserted but no fault happen

CHIA-CHUN,LIN
Prodigy 30 points
Part Number: BQ76952EVM
Other Parts Discussed in Thread: BQSTUDIO

The ALRT_PIN, DDSG_PIN, and DCHG_PIN bits in the FET Status register are asserted. However, no protection or PF trigger has been identified.

Meanwhile, the SSBC, SSA, and PF bits in the Alarm Status register are deasserted (please refer to the attached figure).

I've attached my data memory configuration, which was obtained from bqStudio.

I strongly suspect that the problem may be related to my incorrect configuration since the chip's default settings are functional.

Could someone provide guidance or advice for debugging? Thank you.

myconfig.gg.csv

  • +1
    TI__Mastermind 25760 points

    Hi Chia,

    It looks like the ALERT pin is asserting because the FULLSCAN bit is being set in the Alarm Status register. If any bits are set in the Alarm Status register, then the device will assert the ALERT pin (if it is configured for ALERT mode). This bit is set every time the device completes a full measurement cycle and will stay set until the host processor writes a 1 to that bit in the Alarm Status register (0x62) to clear it. You have the corresponding bit set in the Settings:Alarm:Default Alarm Mask set, which allows the FULLSCAN event to assert the ALERT pin.

    Settings:Configuration:CFETOFF Pin Config [OPT2] cannot be set while [OPT3] is also set. The quick fix for this is changing the setting from 0x3A to 0x2A. The same also applies to Settings:Configuration:DFETOFF Pin Config. It may be due to this that DDSG and DCHG are being asserted.

    Regards,

    Max Verboncoeur

  • 0 in reply to Max Verboncoeur
    Prodigy 30 points

    Hello Max,

    I cleared the FULLSCAN bit, which set the Alarm Status register to 0x0000, and the ALERT pin is now deasserted. Thank you!

    The issue with the latched DDSG and DCHG pins persists even after I changed the CFETOFF and DFETOFF settings from 0x3A to 0x2A.

    Are there any potential reasons that could be causing this issue?

  • 0 in reply to CHIA-CHUN,LIN
    Prodigy 30 points

    Another peculiar issue is that both the [DSG_FET] and [CHG_FET] bits in the FET Status register are deasserted, even though no faults have occurred. This situation results in a drop in the PACK-pin voltage to zero due to the DFET being turned off.

    I suspect that this issue may be related to my previous question about the DDSG and DCHG pins being asserted. However, I still have no clue which setting might be causing this issue.

  • 0 in reply to CHIA-CHUN,LIN
    TI__Mastermind 25760 points

    Hi Chia,

    It's likely that the DFETOFF and CFETOFF pins are controlling the FETs to turn off. What voltage is at the DFETOFF and CFETOFF pins?

    Regards,

    Max Verboncoeur

  • +1 in reply to Max Verboncoeur
    Prodigy 30 points

    Hi Max,

    The voltage on the CFETOFF and DFETOFF pins is approximately 1.8V. Therefore, I adjusted the configuration from 0x2A to 0x06, implementing a weak pull-down to ground to prevent it from floating. Additionally, I set OPT5~OP1 to zero to make it high-impedance. This configuration worked as intended.

    Now, when the CFETOFF/DFETOFF pins are not driven high by the master, the CHG_FET/DSG_FET pins will also be '1', indicating that the CHG/DSG FETs are on. The DDSG pin and DCHG pin behavior aligns with the behavior of the DSG FET and CHG FET.

    However, I believe the behavior of the DDSG and DCHG pins may need to be clarified in the specification. The specification currently states:

    "They provide signals related to protection faults that (on the DCHG pin) would normally cause the CHG driver to be disabled, or (on the DDSG pin) would normally cause the DSG driver to be disabled."

    It appears that the pins may be asserted not only by protection faults but also by the CFETOFF/DFETOFF pin behavior.

  • 0 in reply to CHIA-CHUN,LIN
    TI__Mastermind 25760 points

    Hi Chia,

    I'm glad to hear that you were able to figure it out!

    I believe that the DCHG and DDSG just follow the status of the CHG and DSG FETs rather than the protections triggering.

    Regards,

    Max Verboncoeur

  • 0 in reply to Max Verboncoeur
    Prodigy 30 points

    Hi Max,

    Thank for your help !