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BQ77915: Cell connection sequence issue for stacked implementation?

John M
Expert 2135 points
Part Number: BQ77915

We’re designing a BMS for a 20S pack for a client using four bq7791501 and can ensure that the main BATT- connection is made before the balancing/voltage sensing (C0-C20) connections are made.

But had a concern regarding cell connection order. The C0-C12 balancing/voltage connections will be made (almost) all at the same time via a single connector followed by the C13-C20 connections being made (almost) all at the same time via another connector.

This goes against the recommended cell connection sequence by not connecting each bq7791501’s BATT-/VSS first. There’s a chance that due to pin length tolerances in the connectors that BATT-/VSS for each chip will not be connected at the same time as the other connections and almost never first.

Is this a problem? If yes, how can we connect the balancing/voltage sense lines for a 20S stacked setup without connecting each individually, which would slow down pack assembly a lot? Would we need to add some sort of protection to each VCx pin?

Thank you! Regards, John M.

  • 0
    TI__Expert 8526 points

    Hi John,

    Unfortunately, connecting the upper device cells to their VC pins before the VSS pins are connected could cause damage to the part.  With the proposed connection method, any of the other VSS and VC pins could be connected randomly.  This is a stressful situation even though the BQ77915 is designed with random cell connect in mind (as long as VSS is connected first).  Additionally, the BQ77915's recommended cell input resistors are relatively small, so this will not help to limit current into the VC pins. 

    Connecting cells from the bottom up helps minimize the voltage step applied to the board because the previous cell connected will charge the input filter capacitors, pushing up the cells above that are not connected.  The body diodes of the BQ77915's internal balancing FETs will also push up the unused inputs. 

    Although it will take more time, I recommend connected the cells to the IC in a bottom-up manner.  If this is really impossible, could you potentially try attaching the cells in groups, so the cells for IC 2 will be connected before the cells for IC 3, and then IC 4?  Even with this configuration, I recommend running tests to ensure that the IC will not be damaged.

    TI does not currently have recommendations for alternative circuitry if VSS is not connected first.

    Best,

    Andria

  • 0 in reply to Andria McIntyre
    Expert 2135 points

    Hello Andria,

    Thank you for your quick reply! We were hoping that perhaps zeners be set up from each chip’s VSS to each of the chip’s VCx and VDD pins to provide protection from random cell connection sequencing. But your final line seems to indicate that the answer to that is no. Slight smile

    We might be able to get the client to agree to a new connector setup, 6+6+6+6 pins, instead of 13+8 as used now. But it still doesn’t seem like a good situation for the bq7791501, connecting all pins at once. Sounds like we’d be playing the odds.

    The existing packs are for small PEV’s and have the 13+8 pin connector setup to allow quick factory assembly and pack replacement and upgrades by the dealers. The connector method is necessary (and used by their existing BMS) as the client could never get the dealers to agree to solder in one cell connection at a time when replacing/upgrading packs.

    Regards, John M.

  • 0 in reply to Andria McIntyre
    Expert 2135 points

    Hello Andria,

    If we used separate 6-pin connectors for each chip’s cells (your mention of connecting in groups) and had external balancing FETs so we can have 1k filter resistors (to limit current flow) and differential caps on the VCx inputs could we add differential zeners all adding up to less than the 36V rating of the inputs to handle random cell connection overvoltage? We’d use a 3.3V zener for VC0 and 5V zeners for VC1-VC5 and VDD.

    This way VC0 is limited to 3.3V and no other input can be brought over 36V. Would this prevent damage from a random cell connection sequence?

    Otherwise the only solution we came up with, since connectors must be used (for quick replacement/upgrade), is to have DIP switches on the board that are all opened when connecting or disconnecting the pack. The switches would then be closed in bottom-up sequence to connect the cells in order to the bq7791501’s. Definitely a clunky solution though.

  • +1 in reply to John M
    TI__Expert 8526 points

    Hi John,

    I think your proposed external FET and group connection solution could work.  I also think adding the zener diodes will help to protect the pins.  As long as the datasheet abs max values for the BQ77915 are not exceeded, then there should not be damage to the IC.  I recommend testing this solution thoroughly, though, before large-scale production to ensure its robustness!

    If there are any further doubts about protecting the IC from random-cell connect, then I recommend implementing the switches.

    Best,

    Andria

  • 0 in reply to Andria McIntyre
    Expert 2135 points

    Hello Andria,

    My apologies for the delayed response, I never received an alert for your reply. Thank you!

    We’ll implement the DIP switch solution for all of the prototypes. We’ll also test the group connection method by leaving the switches on for some of the prototypes and we’ll see what happens. Please consider this issue resolved.

    Regards, John M.

  • 0 in reply to John M
    TI__Expert 8526 points

    Hi John,

    Thank you, and best of luck with your project! (:

    Andria