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TPS50601A-SP: What happens if the sync is not present or reactivated during start up, normal function and is reactivated

Axel Detrain
Prodigy 10 points
Part Number: TPS50601A-SP

Dear Sir or madam,

We plan to use 3 TPS50601A-SP to provide (1.2V, 2.5V and 3.3V) power supply for a FPGA in a satellite.

The 3 TPS50601A-SP will normally work in external synchronization mode combined with Sequential Start-Up Sequence or Ratiometric Start-Up Sequence. We are not sure yet which start-up sequence to use.

The 3 TPS50601A-SP will get an external sync signal. I could read that the TPS50601A-SP will use its 500kHz internal switching frequency if the there is no sync during 20us. However, can you tell me:

- what will happen if the external sync is working again? I mean, will the TPS50601A-SP use the external sync as switching frequency again?

- will this sync scenario have an effect on the ratiometric or sequential configuration?

- if we use a ratiometric configuration, will the 3 TPS50601A-SP be switched off at the same time ?

- if we use a sequential configuration, will the 3 TPS50601A-SP be switched off in the reversed order of the start-up?

I am looking forward to hearing from you.

Best regards,

Axel Detrain

  • 0
    TI__Mastermind 28615 points

    Hey Axel,

    If you reapply the SYNC signal the device will in around the same 20 us should synchronize to the applied signal.

    I do have some questions on the second part of your question.
    I assume you have some external circuitry dealing with sequencing the parts.
    What is your concern with how the SYNC pin would change the sequencing?

    One general comment is that the TPS50601A-SP will not stop applying power, thus there wont be any large interruption on the rails.

    Thanks,
    Daniel

  • 0 in reply to Daniel Hartung
    Prodigy 10 points

    Hello Daniel,

    Thanks a lot for your reply!

    The datasheet of the PCGA mentions that the power lines (2.5V, 1.2V and 3.3V) must power up at the same time. If not, there is a power up sequence to follow. For example, 2.5V, then 1.2V, then 3.3V. When the FPGA has to be powered off, the power supply must be powered off at the same time or the reverse sequence of power on. So in this case power off sequence must be 3.3V, then 1.2V and then 2.5V.

    This is the reason why we are not sure whether the Sequential Start-Up Sequence or Ratiometric Start-Up Sequence would meet the requirements of the FPGA power sequence.

    Do you have any experience or advice about ideal startup configuration to meet the power on and power off of the FPGA?

    Thanks,

    Axel

  • +1 in reply to Axel Detrain
    TI__Mastermind 28615 points

    Hey Axel,

    Starting up/shutting down at the same time may be easier than doing any logic to determine the ordering.

    Start-up is the easy part as the TPS50601A-SP has PWRGD pins that can be chained with the EN pins of the next one in order to order the start-up properly.
    However if you want power down, this has to be handled by an external chip that would bring the outputs down in order.

    If the FPGA has an option that allows all the rails to come up and down together, that is the easier option.

    Thanks,
    Daniel

  • 0 in reply to Daniel Hartung
    Prodigy 10 points

    Thank you very much Daniel!

    I will consider this for the design.

    Regards,

    Axel

  • 0 in reply to Axel Detrain
    TI__Mastermind 28615 points

    Welcome!

    Thanks,
    Daniel