TPS6594-Q1: PGOOD is always H, I2C nack

Shinji Mada said:

Question1:

GPIO9 is used as PGOOD in order to monitor with other devices that the PMIC has completed power output.

PGOOD is outputting H regardless of the state in which BUCK/LDO is not output (0V).
It has remained high ever since VCCA/VIO was turned on.

To use PGOOD in this manner, set PGOOD_SEL_NRSTOUT =1. Your current setting have it set to 0 and PMIC is behaving according to the blue line in Figure 8-12. You want it to to behave according to the red line. 

Shinji Mada said:

Question 2:

The PMIC is accessed from the control device via the I2C bus (without CRC).

I am able to write to the register without any problems, but the PMIC is returning a NACK.

Reads the written register and confirms that it was written correctly.

Can this NACK be ignored? Or should I treat it as an access error?

If you are seeing something similar to this at the end, then you it can ignore it. 

HI Michael,

As you pointed out, it worked fine when PGOOD_SEL_NRSTOUT_SOC=1.
(I used nRSTOUT_SOC because nRSTOUT is used for other functions.)
Question 1 is solved, thank you.

About Question2:
The attached waveform is for Read Cycle, right?
It has been confirmed in the data sheet that a NACK is returned during Read Cycle.(Figure.8-59, 8-60)
What I'm concerned about is Write Cycle.
What are the possible causes of a NACK being returned during a Write Cycle?

Thank you.

Shinji Mada said:

The attached waveform is for Read Cycle, right?

Yes, that waveform represents a read cycle.

Shinji Mada said:

What are the possible causes of a NACK being returned during a Write Cycle?

Some possible reasons:

• Host didn’t send enough clocks so it didn’t send the last ACK
• Device was unable to pull low for some reason
• Host is misinterpreting the response frame

Can you provide a scope shot of the write cycle including the NACK?

This waveform is when writing 0x81 bit0 to 1.

The cursor on the right shows NACK.

Before this waveform, 0x9B is written to address 0xA1 , 0x01 is written to address 0x66,

but at that time, an ACK response is received.

Is there anything you notice?

I2C1 address:0x48

ch1:I2C1_SDA, ch2:I2C1_SCL

Do you only receive a NACK when writing to the MISC_CTRL: NRSTOUT bit? I am double checking, but this write might not be allowed.

Yes, NACK occurs only when bit0 is rewritten.

Other answers say that it can be rewritten by writing registers, but do I understand this incorrectly?

TPS6594-Q1: can we control nRSTOUT directly via register MISC_CTRL bit0

Isn't it an R/W register? 　Does it mean that it only accepts settings from PFSM?

Hello Michael,

I understood that there is no problem in ignoring this NACK.

Thank you for your help.