I have a similar question to where the conversation went in the thread listed below. I need to understand the worst-case variation in the HIGH voltage for my application. My understanding is that the HIGH state output voltage is switched from VLDO, but I wanted to:
1. Verify that is indeed the case
2. See if there is a way to better constrain the variation in VLDO that I will actually see in my application (i.e. a specific range of VIN, Tj, Fsync, TID, etc.) as the datasheet min/max range is a bit too wide for my design
