Our TPS38700 design is getting into a FAILSAFE state when we try to power up (by taking ACT high) if we enable the CLK32 output. If we set an Enable to go high in slot 1 we can see it go high after ~10us, then go low again after ~20us. At this point the registers are showing:
I (15413) PwrSeq: Reg 0x13 (CTL_STAT) = 0x0e
I (15423) PwrSeq: Reg 0x10 (INT_SRC1) = 0x04
I (15423) PwrSeq: Reg 0x16 (EN_STRD1) = 0x02
I (15433) PwrSeq: Reg 0x17 (EN_STRD2) = 0x00
nRST is 0 and nIRQ is 0.
This happens if PWR_CLK32OE is not 0x00. The power sequencer appears to work normally if PWR_CLK32OE is 0x00 (i.e. the external 32k clock is not enabled).
Can you explain why F_EN is triggered in this case?