• State TI Thinks Resolved
  • Locked Locked
  • Replies 5 replies
  • Answers 2 answers
  • Subscribers 63 subscribers
  • Views 393 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LM25143: 4 phase output DITH design

Irene Qin
Expert 3395 points
Part Number: LM25143

Hi team

My customer is using 2 pcs LM25143 in 4 phase buck circuit.

6 cell battery （15V-25V）step down to 12V； Outpower :TDC:500W; EDC:600W

Here is one concern:

If the primary controller connect the DITH to GND with Capacitor(enable DITH), but secondary controller floating or connect to GND.

Does secondary controller also enable DITH function?

Cause in my opinion, primary controller as the external clock source of secondary controller should follow the primary controller. 

Please kindly let me know your opinion.

Thanks

  • 0
    TI__Mastermind 22301 points

    Hi Irene,

    You are correct, when using SYNC, DITH is disabled. 

    Because 4-phase uses SYNC, the second controller's DITH is disabled.

    Hope this helps,

    -Orlando

  • 0 in reply to Orlando Murray
    TI__Expert 3395 points

    Hi Orlando

    Thanks for your quick reply.

    But the answer confuse me.

    My opinion is when the primary controller connect the DITH to GND with Capacitor(enable DITH), but secondary controller floating or connect to GND.

    Does primary controller enable the DITH function and the secondary controller DITH function disable?

    irene 

  • 0 in reply to Irene Qin
    TI__Expert 3395 points

    And even thought the secondary controller DITH function is disabled, but due to the clock source (primary controller) already dither frequency, so the frequency of secondary frequency has already been dithered?

  • 0 in reply to Irene Qin
    TI__Expert 3395 points

    Hi sorry for double question

    About the CS and SS, from datasheet:

    SS : the LO gate driver is disabled when the LM25143 internal logic pulls SS low due to a fault condition.

    CS: If the peak differential current signal sensed from CS to VOUT exceeds the current limit threshold of 73 mV, the current limit comparator immediately terminates the applicable HO output for cycle-by-cycle current limiting.

    So my question is why SS pull low disable LO, and CS exceed threshold terminate the HO output? wht not terminate both of LO and HO?

  • 0 in reply to Irene Qin
    TI__Mastermind 22301 points

    Hi Irene,

    1) Yes, the primary will control dithering for all 4 phases. The secondary will not have dither function no matter what (because clock is synchronized in to secondary controller).

    2) If there is a current limit, the LO is turned on to allow the inductor current to decrease. If LO was turned off for current limit, the inductor current would still decrease via low-side FET body diode but that will be higher power losses than just turning on LO.

    If there is a fault condition, the LO is terminated because the device will disable and the inductor current is not monitored.

    Hope this helps,

    -Orlando