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TPS65217: PMIC Power Down Behavior Deviation

Simon Acker
Prodigy 20 points
Part Number: TPS65217
Other Parts Discussed in Thread: TL5209,

Good afternoon!

I am verifying a PCBA design with an OSD3358-512M-ICB C-SIP. This SOM contains a TPS65217C PMIC, TL5209 LDO, and an AM355x Sitara processor. It is my understanding that the power down sequence should be the reverse of the power up sequence. There are a handful of places where the power down sequence of our design does not match the reverse of the power up sequence. I would be grateful for clarification on whether we should be concerned about these variations from the expected behavior. Thanks!

Pin legend: 

  • PMIC_PGOOD -> TPS56217C PGOOD pin
  • PMIC_LDO_PGOOD -> TPS56217C LDO_PGOOD pin
  • PMIC_NWAKEUP -> TPS56217C NWAKEUP pin
  • VDDSHV_3P3V -> TPS56217C LDO4
  • SYS_VDD1_3P3V -> TL5209 Output
  • VDD_CORE -> TPS56217C DCDC3
  • VDD_MPU -> TPS56217C DCDC2

Note: I confirmed that registers 0x19 - 0x1E of the TPS56217C match the reset states for the variant of the IC.

Issues:

1. PMIC_PGOOD, PMIC_NWAKEUP, and PMIC_LDO_PGOOD drop-out behavior. During power-down, these three signals are briefly pulled low before decaying as expected. While not entirely clear in these first scope capture, the drop-out behavior occurs simultaneously for all three signals. In our design, these pins are all connected to pins on the AM355x processor. PMIC_PGOOD is connected to the PWRONRSTn pin, PMIC_LDO_PGOOD is connected to the RTC_PWRONRSTn pin, and PMIC_NWAKEUP is connected to the EXT_WAKEUP pin.

2. VDDSHV_3P3V begins to fall ~3.6 ms before VDD_CORE and VDD_MPU begin to fall. Based on the reverse power-up sequence, I would expect VDD_CORE and VDD_MPU to begin to fall about 1 ms before VDDSHV_3P3V. In our design, VDDSHV_3P3V is connected to 5/6 VDDSHV pins and to an external voltage clamping circuit.

Thank you!

  • 0
    TI__Mastermind 19080 points

    Hi Simon,

    1. Can you share your schematic and layout? I can set up a private message if need be for file sharing.

    2. How are you initiating the power down? It looks like SYS_VOUT is dropping before PMIC_PWR_EN is pulled low. Is power down by UVLO intentional in this case?

    3. What is the SYS_VOUT voltage when you see the PGOOD and WAKEUP signals drop for the first time (before decay behavior starts).

    Regards,

    James

  • 0 in reply to James Steenbock
    Prodigy 20 points

    Hi James,

    Thanks for getting back to me. Your second point is an excellent one. I was testing the power down sequence by shutting off the supply. Using the RTC to pull PMIC_PWR_EN low (via a CLI tool) fixes both of the problems I mentioned above.

    Based on the new waveforms, I've got two points of concern.

    1. VDDS_DDR (DCDC1) begins to fall approximately 1 ms before NWAKEUP and PWR_EN (not captured here). Based on Figure 4 of the TPS56217 datasheet, these signals should be time aligned. On power up, VDDS_DDR rose about 1 ms before NWAKEUP. Is either the power up or power down behavior concerning?

    2. I'm seeing a little bump in the falling edge of VDDSHV_3P3V. I don't believe this is due to any of the external circuitry. Is this cause for concern?

    Thanks so much!

  • 0 in reply to Simon Acker
    TI__Mastermind 19080 points

    Hi Simon,

    1) What is your pull-up source for the PGOOD and WAKEUP signals?

    2) This bump in the output should not be coming from the PMIC since at this point the device is powered down. I would double check that no external devices are influencing the voltage at the output node.

    Regards,

    James

  • 0 in reply to James Steenbock
    Prodigy 20 points

    1. PGOOD and WAKEUP are pulled up to SYS_RTC_1P8V (LDO1)

    2. Will do.

  • 0 in reply to Simon Acker
    TI__Mastermind 19080 points

    HI Simon,

    Thanks for confirming the pull up source.

    Simon Acker said:
    VDDS_DDR (DCDC1) begins to fall approximately 1 ms before NWAKEUP and PWR_EN (not captured here). Based on Figure 4 of the TPS56217 datasheet, these signals should be time aligned. On power up, VDDS_DDR rose about 1 ms before NWAKEUP. Is either the power up or power down behavior concerning?

    Just to clarify, for this test you used PMIC_PWR_EN to trigger the power down? If that's the case, then I'm not sure how DCDC1 could begin shut down 1ms before PWR_EN. The DCDC1 regulator should be operational until PWR_EN is pulled low and detected by the internal circuitry. Based on the wording above it sounds like DCDC1 is powering off before the power down trigger occurs.

    I believe the nWAKEUP signal is only pulled low by the IC when a WAKEUP event is triggered. A fault condition or power down trigger would not cause the internal nWAKEUP FET to pull the pin LOW. The 1ms delay on nWAKEUP is more likely due to the pull-up source being deactivated as part of the power down sequence.

    Regards,

    James

  • 0 in reply to James Steenbock
    Prodigy 20 points

    So it is acceptable for NWAKEUP to fall after DCDC1 if it is pulled to LDO1? That doesn't match the reverse of the timing shown here. If this is acceptable, the timing issue is resolved.

    This is what I meant by PWR_EN falling. It was low for a bit, then rose again before decaying.

  • +1 in reply to Simon Acker
    TI__Mastermind 19080 points

    Hi Simon,

    It is normal for nWAKEUP to decay in your case. The internal nWAKEUP pull-down FET should not activate when power down is triggered, but if the pull-up source for the pin decays then nWAKEUP will also decay. If you are using one of the TPS65217 rails as the pull-up this is expected.

    Simon Acker said:
    This is what I meant by PWR_EN falling. It was low for a bit, then rose again before decaying.

    This PWR_EN behavior should not be an issue. When power down is triggered, there should be a 1s window where the PMIC is in the WAIT MIN
    OFF TIME3 state. It looks like the PMIC_PWR_EN signal decays below VIL threshold well before that window expires, so the device should move to PRE OFF state normally. At that point, the POR sequence will be dictated by other signals (AC, USB, or PB_IN).

    Regards,

    James

  • 0 in reply to James Steenbock
    Prodigy 20 points

    Awesome.

    As for the bump I captured above, do you think it would cause problems with the PMIC or AM355x processor?

  • +1 in reply to Simon Acker
    TI__Mastermind 19080 points

    Hi Simon,

    For the PMIC I don't think the bump would cause damage as long as the voltage doesn't exceed the absolute max voltage rating of the IC pin. For the AM335x I can't say for sure, you would need to ask the Sitara processor team in a thread tagging the AM335x.

    I would be surprised if that bump damaged the AM335x during power down, but you may want to check the current flow and run it by the processor team to be sure.

    Regards,

    James