LM73606: QUery regarding UVLO and alternate solutions

Vijetha HN

Part Number: LM73606

Hi,

We are using LM73606QRNPRQ1 for 24V to 5V conversion. Attached the schematics.

The 24V is given from a custom AC-DC flyback circuit. The 24V ramps up slowly. Hence the 5V is generated before 24V setles down. This intern is powering all the other power supplies and processor tries to boot. So, 24V starts dipping as the load on 24V increased even before it reaches actual 24V. Hence everytime we power cycle the board, the booting does not happen or it gets stuck.

One possible solution for this issue is enabling UVLO feature of the regulator using proper RENB and RENT resistors. But unfortunately in our design EN is connected to 24V through 0 OHM resistor. And we are not in a position to do any change or reworks in the design/board. SO other than UVLO, can you please suggest any othyer feature or solutions that helps us to avoid 5V generation before 24V reaches to actual 24V value? We prefer only BOM changes. Please suggest.

Regards,

Vijetha HN

over 1 year ago

0 Rahil Ajani over 1 year ago

TI__Genius 9460 points

Hi Vijetha,

Could you please send the schematic?

Regards,

Rahil

0 Vijetha HN over 1 year ago in reply to Rahil Ajani

Intellectual 705 points

0 Rahil Ajani over 1 year ago in reply to Vijetha HN

TI__Genius 9460 points

Hi Vijetha,

With the single resistor from EN to VIN, there is no way to implement EN/UVLO precision feature.

The only solution would be a design change or to artificially control EN with an external voltage source and enable it after VIN is 24V with the R171 resistor removed

Regards,

Rahil

0 Vijetha HN over 1 year ago in reply to Rahil Ajani

Intellectual 705 points

Hi,

Option 1 : you think can we do something with SS? Currently we connected 0.01uF resulting in 5mS of SS. If we increase that, can we just delay Power on of 5V loads? If yes, what could be the maximum capacitor we can connect?

Option 2 : Connecting some higher resistor value on R171 will help?

I just want some solution without any change in the design. Whether any of these 2 options make sense? Or do you have any other option?

0 Rahil Ajani over 1 year ago in reply to Vijetha HN

TI__Genius 9460 points

Hi Vijetha,

Option 1 could work. Use C_SS = I_SSC × t_SS (Section 7.3.7 of datasheet) to find the capacitor value. You will need to make sure the ramp up time for Vout is much slower than the ramp up time of Vin.

Option 2 will not work because you need 2 resistors to create a resistor divider.

Regards,

Rahil

0 Vijetha HN over 1 year ago in reply to Rahil Ajani

Intellectual 705 points

Is there any upper limit for the capacitor value or delay with respect to the regulator?

0 Rahil Ajani over 1 year ago in reply to Vijetha HN

TI__Genius 9460 points

I don't see any limits in the datasheet. Theoretically I don't think there should be any limits on this.

Regards,

Rahil

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LM73606: QUery regarding UVLO and alternate solutions