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TPS3899: Behavior when entering small pulse on SENSE pin.

Motoyasu Hattori
Genius 10935 points
Part Number: TPS3899

Hi,

I want to confirm the behavior on TPS3899.

If the pulse (Low->High->Low) whose width is less than tD (Red circle) enters on SENSE pin, TPS3899 /RESET is Low to High (Yellow arrow), after High to Low on this SENSE pin.  Is it correct?

On the case of opposite pulse (High->Low-High), if this pulse width is less than tD enters on SENSE in, TPS3899 /RESET is also High->Low, after Low to High on SENSE pin.   Is it correct?

Assume clock which width is less than tD is entered on SENSE pin, /RESET is also output like clock.  Is it correct?

Please advise us.

Thanks and best regards,
M.HATTORI.

  • 0
    TI__Mastermind 18690 points

    Hattori,

    The TPS3899 has two timing to account for, Td = Reset time delay and Td-Sense = Sense delay. In your first scenario, Low->High->Low, with High duration shorter than Td, RESET will stay low and not de-assert. The case for your second scenario, High->Low->High, with Low duration is shorter than Td-Sense, RESET will not assert. In both scenario, the triggering event has to have a greater duration than the configured timing Td and Td-sense for RESET to assert or de-assert.

    If the high duration of the clock is less than TD, the RESET will stay low.

    Jesse 

  • 0 in reply to Jesse Villanueva
    TI__Genius 10935 points

    Hi,

    At first, I forget to attached the following figure.  I am still confusing.  If the following High pulse (RED circle) is occurred, after High pulse, /RESET is de-assert.  That is why I am asking.   Please let us know your comments.

    Thanks and best regards,
    M.HATTORI.

  • 0 in reply to Motoyasu Hattori
    TI__Mastermind 18690 points

    In the image you provided, The sense pin is connected to the VDD, which turns off the device when the signal hit LOW. The proper behavior is on fig 8-2.

    Jesse  

  • 0 in reply to Jesse Villanueva
    TI__Genius 10935 points

    Hi, Jesse-san,

    I am confusing.   On Figure 8-3, if t<td case, RESET keeps low such as read dotted line.  Is it correct?

    Please advise us.

    Thanks and best regards,
    M.HATTORI.

  • 0 in reply to Motoyasu Hattori
    TI__Mastermind 18690 points

    Hi Hattori,

    Based on the description of this behavior on the DS.

    Since the charge voltage of the CTR is based on the VDD value, when the VDD dropped, the CTR charge threshold lowered as well causing the device to think that it reached the VTH_CTR value which leads to the shorter td and a reset de-assertion.

    Jesse