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UCC28951: Internal RAMP threshold tolerance

Jeff Melvin
Prodigy 170 points
Part Number: UCC28951

The block diagram shows an internal ramp generator creating a 0.8V to 2.8V sawtooth for the PWM comparators inverting input.

Including the offset voltage and hysteresis of the PWM comparator, what are the threshold ranges for the COMP signal?

In other words, if I have RSUM configured for VMC operation and control the COMP pin voltage (to control duty cycle), what voltage on COMP will create a 0% and a 100% duty cycle?  And what are the tolerances of those thresholds?

  • 0
    TI__Guru* 76315 points

    Hello,

    I am reviewing your inquiry.

    Regards,

  • 0 in reply to Mike O'
    TI__Guru* 76315 points

    Hello,

    When the comp is below 0.8 V the converter should be demanding 0% duty cycle when the COMP is above 2.8 V the converter will demand 100% duty cycle.

    I reviewed the data sheet parameters and the comparator thresholds are +/- 3%.  So the tolerance of the PWM slope compensation ramp should track at +/- 3%.

    Regards,

  • 0
    Prodigy 170 points

    I'm guessing these levels are derived from the REF voltage.  If that's true, the ratiometric values relative to REF are preferred.

  • 0 in reply to Jeff Melvin
    Prodigy 170 points

    I'm looking at the datasheet and see no specs regarding the PWM ramp.  Can you please provide the spec that indicates the ±3% tolerance?

    Also, as stated in my previous response, if the ratiometric tolerance with respect to REF is lower (or higher), that would be valuable information.

  • 0 in reply to Jeff Melvin
    TI__Guru* 76315 points

    Hello,

    I am reviewing your inquiry and will get back to you shortly.

    Regards,

  • 0 in reply to Mike O'
    TI__Guru* 76315 points

    Hello,

    You are correct that the data sheet does not have specifications on the PWM ramp nor is the accuracy tested. The reason for this is the voltage amplifier feedback will correct for any errors in the PWM ramp.  However, when you review the other specifications you can get an estimate of how accurate the PWM ramp is.  In this case I looked at the cycle by cycle peak current limit to estimate the accuracy of +/- 3%.  

      

    Regards,

  • 0 in reply to Mike O'
    Prodigy 170 points

    Thank you for that confirmation... I assumed that was your intent.

    I am going to have to justify my implementation in a design review.  Is it fair to say that the PWM ramp switching voltages are based on a divider driven by the REF voltage, in the same way the cycle-by-cycle peak current limit is done?

    My testing (on only one device so far) indicates the output duty cycle is 2.87% (min, due to TMIN) with COMP = 0.8974V, 50.21% with COMP = 1.8358V, and 97.60% (max) with COMP = 2.8373V.

    So the equation for this device is:  COMP = 0.838628 + 2.04782 * DutyCycle  -- or --
                                                            DutyCycle = (COMP - 0.838628) / 2.04782
         with a 3.11% error at 50.21%

    I feel good about my results (on this single part), but your response will certainly help during my design review...

    Thank you,
    Jeff

  • 0 in reply to Jeff Melvin
    TI__Guru* 76315 points

    Hello,

    I am reviewing your inquiry and will get back to you shortly.

    Regards,

  • +1 in reply to Mike O'
    TI__Guru* 76315 points

    Hello,

    I do believe the internal dividers and offsets on the comparator contribute to the accuracy of the ramp.  However, after reviewing the data sheet further there is a frequency oscillator test specification of  100 kHz.  So the accuracy of the oscillator ramp based on these numbers is roughly +/- 8%.  So this error would be affected of the tolerance of the reference and internal timing components as well.

    Ideal Comp to control duty cycle = 0.8 V + 2V*D

    Worse Case Comp variation to control duty cycle = 0.8V*0.92 +2*V*1.08*D 

    Regards,

  • 0 in reply to Mike O'
    TI__Guru* 76315 points

    Hello,

    The voltage amplifier in the UCC28951 has a common mode range of 0.5 to 3.6 V.  This range should enable the voltage amplifier to control the duty cycle of the PSFB despite the errors in the internal PWM ramp.

    Regards,

  • +1 in reply to Mike O'
    Prodigy 170 points

    I would agree with your assessment, BUT if this is true Figure 7-9 is misleading.  Figure 7-9 shows the oscillator and ramp generator as separate entities, but surely the ramp generator feeds back to the oscillator.

    I'd also say the worst case COMP variation is a little larger at 0.8V*92% to 108%*2.8V -- or -- 736...3024mV.

    Thank you for your help!
    Jeff