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Hello,
Please clarify the Tpd with respect to Vt SENSE trip to RESETN asserted delay.
From the spec of the device TPS3808E-Q1
Or TPS3808-Q1
for the typical Tpd delay is 20-30us and maximum of 50us.
Whereas the EVM board, reference Figure 14 :
The Tpd delay is about 20ms given the SENSE is 0.405V and more if any other V SENSE.
How do you explain the discrepancy between the device spec sheet and measurement of EVM board ?
If so could you confirm the spec is guaranteed of 50us maximum delay ?
Please note that the Tpd delay of MR\ to RESET\ is within the spec according to the measurement of EVM board.
Hi Hyunh,
It is hard to say when the Vsense crosses the threshold from this image since it is zoomed out. I will replicate in the lab, I will give you an update within 24 hr. As for the 50us maximum delay, Ti guarantees any data and value present in our datasheets.
Jesse
Hi Hyunh,
Above is a scope image of my bench testing of the TPS3808. During my testing, I have seen the reset sense delay fluctuate between 10us and ~1us.
The test was ran in room temperature.
Jesse