TPS7H5001-SP: Maximum Leading Edge Blanking (LEB) time

Chad Whiteley

Part Number: TPS7H5001-SP

Hello,

According to the device datasheet, the maximum resistor value that should be used to program the LEB is RLEB = 300k. I calculate that this should result in LEB of approximately 255ns (not including internal logic delay).

Is it possible to get a little more information on this limitation, and what the possible outcome would be if I used a higher resistance (say 475k, to try to achieve LEB of 400ns)?

Thanks
Chad W.

over 1 year ago

+1 Daniel Hartung over 1 year ago

TI__Mastermind 28605 points

Hey Chad,

The TPS7H5001-SP was designed to be optimal in the range we state.
While the device may accept a higher resistance and make a higher LEB, we would not suggest it.

One issue I imagine you would run into is the accuracy of the equation for LEB and the accuracy of the part to part variation of LEB above 300k values would be poor

Thanks,
Daniel

0 Chad Whiteley over 1 year ago in reply to Daniel Hartung

Prodigy 50 points

I see, thanks Daniel.

As a follow up question: do you have any recommendations for evaluating the actual tmin (in hardware test)?

In my current test setup at light load (when pulse skipping occurs) I sometimes see very short duration pulses (although I'm not sure they exhibit tmin).

Alternatively I was thinking of looking at the first few pulses during soft start (have not tried that yet).

Thanks for your input,
Chad W.

+1 Daniel Hartung over 1 year ago in reply to Chad Whiteley

TI__Mastermind 28605 points

Hey Chad,

Generally the easiest way to is slowly increase the COMP voltage until you see pulses when you have a voltage ramp on CS_ILIM.

Remember that tmin = LEB+min on time.

Thanks,
Daniel

0 Chad Whiteley over 1 year ago in reply to Daniel Hartung

Prodigy 50 points

Aha, thanks again.

I'm not terribly familiar with transconductance amplifiers. In general, is it safe to supply voltage to the output from an external supply (within the max limits of the device)? I'd be worried about a "traditional" op-amp potentially sinking too much current, maybe not the case for the OTA used here.

Thanks!
Chad W.

+1 Daniel Hartung over 1 year ago in reply to Chad Whiteley

TI__Mastermind 28605 points

Hey Chad,

We regularly bypass our error amplifier in testing.
We would suggest you stay within the voltage limits of the pin, but outside of that I have not run into issues.

Thanks,
Daniel

0 Chad Whiteley over 1 year ago in reply to Daniel Hartung

Prodigy 50 points

Great, thanks again for all of the info!

-Chad W.

0 Daniel Hartung over 1 year ago in reply to Chad Whiteley

TI__Mastermind 28605 points

Welcome

Daniel

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TPS7H5001-SP: Maximum Leading Edge Blanking (LEB) time