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TPS65219: Power Down Sequence - Deglitch Timing

Nicholas Fournier
Prodigy 70 points
Part Number: TPS65219
Other Parts Discussed in Thread: TPS65220,

I am interested in using this PMIC with the AM64x processor. Specifically the TPS6521901 version. There seems to be conflicting information or unclarity in the documentation available for this product that does not match. I would like to break my question into parts:

  1. I am trying to understand the time delay between when the OFF request is made and when the TPS6521901 actually begins the power down sequence.

    1. In the application note "Powering the AM64x with the TPS65220 or TPS65219 PMIC" (SLVAFE9.pdf) in figure 4.6 on page 11 it shows "tDEGLITCH=8s" in the power down cycle diagram.
      However, according to the datasheet for the TPS65219: "10.3.1a tDEGLITCH Fault Detection Deglitch Time for Under Voltage (UV) and Short to GND (SCG)" which seems to indicate TDGLITCH is only applicable to under-voltage and not to OFF request?

    2. In the technical reference manual for the TPS6521901 the power down cycle diagram shows the delay labeled as "tDEGL_OFF" but this value is not defined in either the technical reference manual or in the datasheet

    3. According to the datasheet "The power-down sequence starts if the EN input is below the VIH-threshold for tDEGL_EN_Fall" and the datasheet indicates tDEGL_EN_Fall = 70us
      However, this threshold is not mentioned in the technical reference manual or the application note.

  2. I am trying to confirm how the PMIC manages the power down sequence when VSYS disappears. In all of the power down sequences there is an OFF request and the PMIC powers down all rails prior to VSYS, but what about when VSYS shuts down unexpectedly? According to the technical reference manual EN_PB_VSENSE is configured as "enable" (not as VSense). So when the datasheet says "7.3.2 Power-Down Sequencing An OFF-request or a shut-down-fault triggers the power-down sequence" I understand this to mean "depending on configuration" because it can be one or the other but not BOTH? It can be either an enable/OFF request or it can be shutdown-fault from VSense?

    The TPS6521901 does not have VSense enabled, but even if it did, the recommendation is to monitor power from the pre-regulator to VSYS but what is recommended when only VSYS is available and the pre-regulator is off-board?

  3. Separate note about missing information:
    In the technical reference manual for TPS6521901 it says regarding EN_PB_VSENSE_DEGL value 0x0 "short (typ: 120us if configured as EN or VSENSE)"
    In the datasheet on the other hand it says "0h = short (typ: 200ms if configured as PB) 1h = long (typ: 50ms if configured as EN or VSENSE)"
    The datasheet does not specify the description for 0h (0x0) in the condition of configured as EN
  • 0
    TI__Mastermind 22541 points

    Hi,

    Thank You for using our E2E forum. We will review the request and provide an update within the next 24Hrs.

    Thanks,

    Brenda

  • 0 in reply to Brenda Diaz
    TI__Mastermind 22541 points

    Hi Nicholas,

    Thanks for your patience. Please find the feedback below and let us know if you have any questions or need additional information. 

    • The EN/PB/VSENSE pin of the TPS6521901 is configured as "Enable" with short deglitch (120us typical) and first supply detection (PU_ON_FSD = 0x1). Please refer to the TPS6521901 Technical Reference Manual (https://www.ti.com/lit/pdf/slvuch3) for additional information about the NVM settings that were released to production. The AM64x Apps note was released before the device was release to the market and we are taking the corresponding actions to update the information. 

    • The ON-request deglitch is configurable but the OFF-request deglitch is fixed. For non-configurable settings, please refer to the device data sheet. When the EN/PB/VSENSE pin is configured as "Enable", the OFF deglitch is 70us typical (tDEGL_EN_Fall).

    • When the pre-regulator that supplies the PMIC is suddenly disconnected, it is called an uncontrolled power-down. In this scenario, VSYS goes below the UVLO threshold and PMIC is turned OFF, unable to control the power down sequence. PMIC can't stay ON or control anything if it doesn't have a valid supply voltage. An OFF request must be triggered by hardware (by pulling the EN pin low) or by software (I2C_OFF_REQ) before the pre-regulator is disconnected.  

    Thanks,

    Brenda