Hi all,
I trying to implement PSFB converter with UCC28950 IC. I am giving 12V bias separately and the input voltage(400V) through a Bridge Rectifier Circuit.
When the bias 12V is given, the QA, QB, QC, and QD are showing pulses of nearly 50% duty ratio. However there are no pulses for switching the secondary devices (QE, QF).
The Vref value is 5V, SS/EN is also 5V.
What could be the issue for the circuit not turning on.
What other parameters need to be checked for troubleshooting.
Thanks
Hello,
I actaully made a mistake in my calculations based on previous information. The clamp would have been set at 218 V roughly. However, your latest information is based on 54 V output and not 48 V.
So the clamp would be at a different voltage would ber
Vclamp = (Iout +dIL/2)*R8 + Vout*2 + VD6
dIL = 6.25 A according to your excel file.
Iout = 450W/54V = 8.33A
Vclamp = (8.33A +6.25A/2)*(10 ohm)+54*2+1.5V = 224V
If CH1 is 50 V per division the voltage rings up to roughly 430V. This would indicate the clamp is not working the way it should.
You might want to check the voltage across R8 to see if it is indeed 54V*2 = 108 V. Capacitor C1 may not be connected or damaged.
If the voltage across C1 is correct you may want to check R8 to make sure that it is not damaged. Lastly you may want to check the SR FET drain current to make sure it is what it is supposed to be.
Regards,
In continuation with above post. Today I tested with RCD Clamp with R=550Ohms, C=0.094uF (Though this was obtained for clamping at 230V, with leakage as 2uH)
The transformer was also changed to ETD49 with primary magnetizing inductance as 3mH. The leakage measured is (Secondary half 1: 464nH and Secondary Half 2: 765nH). The waveforms obtained are attached.
There is only one peak which is very sharp at around 350V rest of the waveform is getting clamped around 250V.
My queries are
a) Is this a single 350V peak (measurement error)? Nevertheless, the snubber resistance started heating (the power of snubber resistance is around 15W, The calculated value is ).
b) Will the Loss in the RCD clamp reduce once Synchronous Rectification is enabled? So should I proceed with testing at higher power levels? Presently its around 450W. I need to test at 1500W.
c) What is the preferred winding arrangement? I am using (Primary Half (15 Turns), Secondary 2 (6 Turns), Primary Half (15 Turns), Secondary 1(6 Turns) with the secondary (S1) closest to the core limb). The primary halves are connected in series.
Hi Mike,
Sorry for the late reply. During the testing the devices got damaged twice. In one instance the clamp diodes D4 got damaged. I had used 600V,3A SMD ultra fast diode. However, Now i have used 600V, 6A diode with TO-220 Package. Now i am able to get regulation at 48V with input around 330 onwards. However, I am confused whether the delays are correct and whether softswitching is happening. The switching frequency is reduced to 50kHz
Ch 1: Drain to Source Voltage Primary Device, Ch 2: Drain to Source Voltage Primary Device
Ch 3: 100V scale: Secondary Drain to Source Voltage, Ch 4: Input Current
Ch 1: Input Voltage , Ch 2: Transformer Primary (CYAN)
Ch 4: Input Current
Is the transformer waveform correct?
How do we see if soft-switching is happening , if we don't have access to switch currents.
what should a DESIGN_1500W_48V_22_12_2023_NEW_CONTROL_CARD_UPDATED_LEAKAGE.xlstypical delay be set. I am presently using the following design values as per attached excel sheet.
Hello,
The excel tool will give you the initial delay settings. I would suggest loading the supply at 10% and fine tune the turn on delays.
The following link will bring you to an application note that describes how to setup the timing.
https://www.ti.com/lit/pdf/slua560
The current in your transformer does not look correct. Maybe the timing in the SRs is off. First try to disable the SRs to see if the transformer current improves.
Regards,
The value of RDELAB and RDELCD and RDELEF is increased to 47k, 47k and 23k Respectively
The gate waveforms of primary side is shown below
The current waveform is still showing spike after increasing delay also
Ch1: Q2 Drain, Ch2: Current,Ch3: Transformer,Ch4: Secondary QE GATE
After disabling synchronous rectification, there is still spike in the current waveform, I am attaching the waveform
This is after disabling SR more (DCM pin connected to VREF).
The EVM module from TI is having the following waveform
what else should be checked to resolve current spike.
Thanks
Thanks Mike for your support even though its Christmas season.
I have a doubt regarding the TABSET and TAFSET calculations. In order to simply the issue of this peaky current , I thought I would increase the TABSET , but keep it fixed. So used a value of 47k for both RDELAB and RDELCD=47k. Shorted ADEL and ADEL to ground.
The input current spikes did not go. Also now there is some notches in transformer.
The value for RDELEF was chosen as 24k. However based on the equations in the datasheet.
I am getting
ns
when RAB=47k , KA=0,CS=0;
For TAFSET i am getting
ns
REF=RDELEF=24k
Even if i use REF=90k (the allowable range mentioned in the datasheet is 13k to 90k), the max delay is 166n.
So how do i set TAFSET=0.5*TABSET. iF the TABSET is 900ns .
Is there anything else in equation which i am missing.
