Hi all,
I trying to implement PSFB converter with UCC28950 IC. I am giving 12V bias separately and the input voltage(400V) through a Bridge Rectifier Circuit.
When the bias 12V is given, the QA, QB, QC, and QD are showing pulses of nearly 50% duty ratio. However there are no pulses for switching the secondary devices (QE, QF).
The Vref value is 5V, SS/EN is also 5V.
What could be the issue for the circuit not turning on.
What other parameters need to be checked for troubleshooting.
Thanks
The Daugther board is oriented so that the pin matching occurs between that in power board and daughter board.
Hello Mike,
There was gate driver issue which was sorted. Now the switches are being driven by pulses. However, there is still negligible output at around 100V. Also the transformer is making some sort of clicking noise. I am attaching the waveform observed in AC side of primary transformer
It seems to operating in burst mode. However, why are the pulses bipolar.
The reference document is attached. Here the DCM connection given is different from that mentioned in the excel tool diargram.
In continuation with above. It seems, for when the Input DC voltage is low (20V input) the system is operational (all four primary devices) pulses are there contin
uously. After that it goes into some burst mode or some protection mode.
After the input voltage increases beyond say 35V. it happens to be in burst mode/protection mode.
What should be the signals I should check for trouble shooting this issue
Hello,
The design is probably audible because it is bursting. The bursting could be caused by a loop stability, noisy CS signal or poor layout.
The following link will bring you to an application note that you can use to help review the design. It goes through the step by step design process of using the UCC28950 in a PSFB. Within the application note there is an excel design tool that can help you review the design as well.
https://www.ti.com/lit/an/slua560d/slua560d.pdf
The information in the application note was used to design the 600 W evaluation module, TI part number UCC28950EVM-447. You can find the user's guide for this evaluation module in the below. There are waveforms and performance data that you might find useful in the User's guide as well.
https://www.ti.com/lit/ug/sluu421a/sluu421a.pdf
It might be worth your while to order the 600 W evaluation module to evaluate it. You can use it to compare waveforms in your existing design and can find it at the following link.
After checking the design with the application note/excel tool, If everything is O.K. you can start to trouble shoot the design.
Troubleshooting your design.
1.) You could have a voltage loop instability. Start by checking this with the excel design tool to see if your theoretical compensation is correct.
2.) Start by evaluating your design up at a light load with SRs disabled.
a.) This can be done by tying the DCM pin of the UCC28950 to the UCC28950 Gnd pin.
3.) I would monitor the UCC28950 's voltage amplifier output, CS pin, SS pin and the primary of the transformer with a differential probe.
a.) Start at 10 % load check for:
- Voltage amplifier output stability
- Check to make sure the CS signal is clean without noise
- Make sure the design is not going into over current hiccup mode protection. The following section from the data sheet explains the cycle by cycle and hiccup mode over current protection and how it works.
4.) Once you have the design working at light loads you set the delay timing based on the application note discussed above.
5.) Once the timing is set you could bring up the design slowly to see if works at greater loads and trouble shoot as necessary.
6.) Once the design is working without the SRs, you can enable the SRs and bring the design slowly up again from light load to full load slowly.
Regards,
Hello,
If your transformer input voltage is a square wave most likely the design is trying to achieve 100% duty cycle. The comp voltage being at 4 to 5 V is the voltage amplifier demanding a 100% duty cycle. You need to adjust the transformer turns ratio to support your design. 5.25 is not large enough.
1. What is your input and output power requirements for your design?
2. Can you share your latest schematic for review?
3. Did you have a chance to review application note slua560d?
a.) Many designers have found this application note helpful in there design process.
b.) It gives calculations for the transformer turns ratio. I believe adjust this turns ratio will help your desired output voltage.
https://www.ti.com/lit/an/slua560d/slua560d.pdf
4. Inside the application note there is a link to the the excel design tool. You can find this link below.
a.) The calculations are based on the application note
https://www.ti.com/lit/an/slua560d/slua560d.pdf
b.) You enter your design parameters in yellow
c.) The excel will then calculate the component values you need for the design in white.
You select components for the design within +/- the calculated vales.
d.) This tool will also compensate the voltage loop for you as well.
Regards,
Hello,
The excel file you have attached is setup for a 12 V output. Is this correct excel file you meant to attach?
If the loop in not compensated correctly you could run into stability issues. This generally will show up as ringing and not bursting. Or sinusoidal oscillations.
I don't think this is the issue. However, you should compensate the loop based on your input and output power requirements. The excel tool will help you compensate the voltage loop.
If you did not change your transformer turns ratio in your design to regulate 36 V at 200 V would require 95% duty cycle. If you are at 30% load you should not be hitting light load burst mode. However, you could be over current hiccup mode protection. This is also a burst mode protection. The following describes how hiccup mode protection works.
Regards,
Hi Mike,
I am attaching the current sense network voltage and also actual current.
CH1: CS pin voltage
CH2: Current Measured
Ch3: Drain to source voltage of Primary Switch
Ch4: Output Voltage
Its observed the current spike is going to higher level about 10A. However, the flat level is around 3 A or so.
CH1: Transformer voltage
CH2: Current Measured
Ch3: Drain to source voltage of Primary Switch
Ch4: Output Voltage
Its observed the current spike is going to higher level about 10A. Howver, the flat level is around 3 A or so.
As it reaches regulation voltage, some noise is observed from transformer side.
The devices are rated for 650V and 44A.
Earlier, I think the devices were damaged due to ringing.
It is seen that around 130Vin, the Output reaches 24V. Now should I directly apply Vin=200, or ramp Vin from 130 V to 200 V and above.
The load is around 300W.
In continuation with above, as there was current spikes during switch transition, I increased the low pass filter Capacitor value to 1nF of CS network. Now, the system seems to be regulating as the transformed voltage is now showing decrease in pulse width when the input voltage is increased.
However, the secondary snubber circuit resistor is getting heated. I am attaching the specific resistor in circuit diagram. Is there any design process for selection/design of snubber or what else is the issue.
Also Presently, I have disabled synchronous rectification, should I enable it now or enable it after resolving the secondary side snubber circuit issue .
Hello,
I reviewed your waveform and the CS pin is a 500mV when the drain current is at 2.5 A.
The way your CT is setup the controller should go into cycle by cycle current limit when the drain current reaches 10 A and the CS pin reaches 2V.
So it seems that your current sense transformer and CS resistor are selected to go into cycle by cycle current limit at 10A.
You have these leading edge current spikes in the drain of the FET that should not be there.
On the below waveform it is roughly 8 A. This indicates that an SR is on when it should not be.
This could indicate and SR timing problem.
I would disable the SRs to see if you can remove this leading edge spike.
The below waveform that you took shows that peak current every other switching cycle is at different level.
This should not happen in peak current mode control.
You used an RSUM resistor of 130 k which should give you a slope compensation of 40 mV/us roughly. For a 10 us period this give you a slope compensation ramp max of 400 mV. So your slope compensation is setup correctly. This issue is most likely a small signal instability. You should recheck your voltage loop compensation.
In your last correspondence you had mentioned the snubber resistor was getting hot? Could you tell me which resistor are getting hot? You have snubbers across the SR FETs and a RC clamp on the output.
Regards,
Hi Mike,
Thanks for the reply. Up till now all the waveforms taken don't have any Synchronous rectification.
a) I have put in red rectangle. the resistors which are getting hot, I have used snubber resistors as 1206 package. Is it getting hot due to lack of synchronous rectification. What is the design process.
b)Also I have put in my last post, that now system is look to regulating the output after putting the filter capacitor of C=1nF in the CS network.
c) Should I change the feedback capacitor , so that regulation is nearly correct at 48 V at say 50% load and then turn on synchronous rectification or should I valid date synchronous rectificaiton at 24V and then proceed to testing at 48V.
Hi Mike,
Thanks for the reply. I am not testing with output of 48V and load around 450W. The design target as mentioned earlier is 1500W,48V.
As you suggested I changed the RCD Clamp to R=10 Ohm, C=470nF, and Rparallel to C as 68k. However, I am not sure if its optimized.
I am attaching the waveform of secondary drain to source voltage, when the output voltage is at 48V. and Input at 340V.
The devices used in secondary side is also same as that used in primary. (Rated at 650V, 44A).
However, the secondary snubbers are getting heated (after running for around 30-40s)
I am using SMD resistors and cap (1206) package. Should I increase the capacitance to mitigate ringing. Also how to manage the heat dissipation.
In primary also I had to use snubbers (1nF, 22Ohm/2W). This also gets heated after 30-40s.
What should be done to reduce heating in snubbers, how do I validate soft switching is happening.
The waveforms along with primary and secondary drain to source and input voltage, output voltage is attached for your reference,
Ch 1: Secondary Side Drain to Source Voltage
Ch 2: Primary Side Drain to Source
Ch 3: Input Voltage
Ch 4: Output Voltage
what should the typical range for the Resistor R8 in attached figure also what is the VD6 assumed.
I assumed Vfet as 250V (even though presently I am using higher rated device). VD6=1.5V, Vout=54 V( Max)
This is the equation
Is there something wrong in assumtion.
