• State TI Thinks Resolved
  • Locked Locked
  • Replies 7 replies
  • Answers 3 answers
  • Subscribers 63 subscribers
  • Views 396 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TPS6594-Q1: Shutdown TPS6594133A when system power is turned off

Daisuke Maeda
Guru 20205 points
Part Number: TPS6594-Q1

Our customer wants to trigger an orderly shutdown for AM69x by turning off the system power, i.e. dropping the supply voltage to the VCCA.

How can an orderly shutdown be triggered?

When VCCA drops below the VCCA_UVLO threshold, the device shuts down all rails except the LDOVRTC,and enters the BACKUP mode. In this case, an immediate shutdown will be triggered instead of an orderly shutdown.

The undervoltage threshold for VCCA can be set by VCCA_UV_THR for PGOOD (GPIO9), but PGOOD is used to turn on/off the 3.3V supplies that ramp down at the end. So the ENABLE pin should not be controlled by the PGOOD pin.

Does the ENABLE pin need to be controlled using a voltage detector IC which monitors the system power supply or VCCA?

Best regards,

Daisuke

  • 0
    Guru 20205 points

    Dear TI support team,

    Thank you for your support. Our customer is waiting for your reply.

    Please give me an answer as soon as possible. Your prompt reply would be appreciated.

    Best regards,

    Daisuke

  • 0
    TI__Mastermind 25725 points
    Daisuke Maeda said:
    Does the ENABLE pin need to be controlled using a voltage detector IC which monitors the system power supply or VCCA?

    Connecting the PMIC's Enable pin to the PG of the 5V or 3.3V Vsys is the recommended practice. 

  • 0 in reply to Michael Gambrill
    Guru 20205 points

    Hi Michael-san,

    Thank you for yor reply.

    Michael Gambrill said:
    Connecting the PMIC's Enable pin to the PG of the 5V or 3.3V Vsys is the recommended practice.

    A voltage detector IC which monitors the Vsys power supply will be used to control the ENABLE pin because the Vsys power supply does not have a PG.

    Our customer wants to know the threshold voltage for a voltage detector IC to control the ENABLE pin based on the Vsys supply voltage. The threshold voltage will be determined by considering the Vsys power supply voltage, the VCCA_UV voltage level, power outputs voltage, etc.

    Since LDO2 is configured as a 3.3V output by default in TPS6594133A, VCCA, PVIN_Bx and PVIN_LDOx will be powered by 5V. If LDO2 is not used as a 3.3V output, VCCA, PVIN_Bx and PVIN_LDOx may be powered by 3.3V.

    Q1. If LDO2 is used as a 3.3V output, can VCCA, PVIN_Bx and PVIN_LDOx be powered by a voltage greater than 3.3V and within 3.6V instead of 5V?

    In the recommended power-down sequence with an OFF request, LDO2 as a 3.3V output is turned OFF last after a 3,500 us delay.

    Therefore, there is a concern that the supply voltage to VCCA and PVIN_LDOx drops, causing the LDO2 output to drop before it is turned off by the sequencer.

    Q2. What is the supply voltage to VCCA and PVIN_LDOx for LDO2 to maintain 3.3V output?

    Must be above the VCCA_UV voltage level for the device to power up properly. For TPS6594133A, when voltage is first applied to VCCA that is greater than VCCA_UVLO, the PMIC sets VCCA_VMON_EN high and sets VCCA_PG_SET to 3.3V or 5V based on sensed VCCA voltage.

    Q3. Does the VCCA_UV voltage level depend on VCCA_UV_THR and/or VCCA_PG_SET in the VCCA_PG_WINDOW register?

    If the VCCA_UV voltage level depends on the VCCA_PG_SET set based on sensed VCCA voltage, it will be very different (3V or 5V).

    Q4. How is the VCCA_UV voltage level determined?

    Best regards,

    Daisuke

  • 0 in reply to Daisuke Maeda
    TI__Mastermind 25725 points

    I will follow up on this today.

  • 0 in reply to Daisuke Maeda
    TI__Mastermind 25725 points

    Hello,

    The TPS6594133A can accept a VCCA centered at 3.3V or 5V. When power is first applied to VCCA, the PMIC starts with VCCA_PG_SET = 5V and LDO2 configured as a normal LDO. If PMIC senses that VCCA is centered at 3.3V, the PFSM will change VCCA_PG_SET = 3.3V and configure LDO2 to be in BYPASS mode acting as a load switch (LDO2_BYPASS = 1).

    With the above statement in mind...

    Daisuke Maeda said:
    Since LDO2 is configured as a 3.3V output by default in TPS6594133A, VCCA, PVIN_Bx and PVIN_LDOx will be powered by 5V. If LDO2 is not used as a 3.3V output, VCCA, PVIN_Bx and PVIN_LDOx may be powered by 3.3V.

    VCCA, PVIN_Bx, and PVIN_LDOx can be powered by 3.3V even if LDO2 is used. If powered by 3.3V, the PMIC's PFSM will configure LDO2 to act as a load switch.

    Daisuke Maeda said:
    Q1. If LDO2 is used as a 3.3V output, can VCCA, PVIN_Bx and PVIN_LDOx be powered by a voltage greater than 3.3V and within 3.6V instead of 5V?

    Technically, this is possible but not recommended. The VCCA PG window will be +/- 10% centered around 3.3V. So the upper limit or VCCA will still be 3.63V. Also, LDO2 will be in load switch mode so the extra head room isn't necessary.

    Daisuke Maeda said:
    Q2. What is the supply voltage to VCCA and PVIN_LDOx for LDO2 to maintain 3.3V output?

    VCCA and PVIN_LDOx should be 3.3V or 5V to maintain 3.3V output.

    Daisuke Maeda said:

    Q3. Does the VCCA_UV voltage level depend on VCCA_UV_THR and/or VCCA_PG_SET in the VCCA_PG_WINDOW register?

    If the VCCA_UV voltage level depends on the VCCA_PG_SET set based on sensed VCCA voltage, it will be very different (3V or 5V).

    Yes the VCCA_UV voltage level depends on VCCA_UV_THR and VCCA_PG_SET. As stated earlier, the PMIC will control VCCA_PG_SET based on what was sensed on initial power up.

  • 0 in reply to Michael Gambrill
    Guru 20205 points

    Hi Michael-san,

    Thank you for yor reply.

    Michael Gambrill said:
    VCCA and PVIN_LDOx should be 3.3V or 5V to maintain 3.3V output.

    For the recommended power-down sequence, the input supply voltage must be maintained above each power output voltage plus the dropout voltage until each power output is turned OFF.

    For BUCK regulators, the dropout voltage (VDROPOUT_Bn) which is input and output voltage difference is 0.7V (MIN).

    If the minimum level of PVIN_LDOn is lower than the dropout voltage of the LDO regulator in addition to the configured LDO output voltage, the output voltage droops to near the PVIN_LDOn level. LDOs will have lower dropout voltage in bypass mode.

    What is the dropout voltage of each LDO?

    Best regards,

    Daisuke

  • 0 in reply to Daisuke Maeda
    TI__Mastermind 25725 points

    In LDO mode, LDOs 1,2, and 3 have guaranteed accuracy when PVIN_LDOn is more than 300mV above the LDO output voltage point. 

    While in bypass mode, the BYPASS resistance determines the amount of drop from input to output: