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TPSM82821: Ripple during power save mode

Jennifer Stander
Intellectual 510 points
Part Number: TPSM82821


Hi,

The datasheet for this part family slows a ripple plot for the device in PWM mode.

It makes a statement that in PWM mode ripple is minimized. 

It indicates that adding decoupling can minimize the increase in power saving mode but does not quantity this. 

Do you have any information about how much more the ripple there will be in power save mode?

I want to use this supply to drive the VDD of a microcontroller with tight supply tolerances. 

Is this device suited for applications like microcontroller core voltages where current demands may change rapidly?

Thank you, 

Jennifer

  • 0
    TI__Expert 8756 points

    Hi Jennifer,

    In principle, the ripple is higher during the power save mode as compared to PWM mode. Figure 9-77, 9-79 and 9-80 shows the output voltage ripple and load transients performance of the devices. Does this help to understand the behaviour better? In addition, the output ripple can be minimized by increasing the decoupling capacitors at the output, however, keeping the maximum within limits specified in the datasheet.

    You can also use the forced PWM version of the device mentioned in the device comparison table in page 3 of the datasheet. This will operate at PWM mode only irrespective of the load current.

    Furthermore, you can also use the PSPICE model or Webench model available at https://www.ti.com/product/TPSM82821 to evaluate the device performance in detail to verify if this meets the microcontroller specs. 

    Let me know if this helps. Thanks!

    BEst regards

    Sneha 

  • 0 in reply to Sneha
    Intellectual 510 points

    The figures you refer to are for forced PWM mode. 

    There is no maximum ripple defined in the data sheet. What limits are you referring t when you say keeping tthe maximum within the limint specified?

    I do not have a PSPICE simulator will the model run in LTspice or TINA?

    I tried to open it with TINA but it did not like it, maybe I just need instructions?

    The Webench model only show information for forced PWM mode. 

    I have an application with extreme area constrains and adding the 2 resistors and 1 capacitor needed for forced PWM mode is problematic. 

    Please quantify how much ripple will increase in power save mode. I don't need exact figures just a ball park 1% 10% 100% , etc...

    OR how much more decoupling do I need to maintain equivalent performance, again just a ball park.

    Thank you,

    Jennifer

  • +1 in reply to Jennifer Stander
    TI__Expert 8756 points

    Hi Jennifer,

    The output ripple shown in Fig 9-77 is in PSM mode. See below figure. This is for 25mA load current and  aprrox 12mV p-p.

    You can download the free software for PSPICE for TI from the product information page here. https://www.ti.com/product/TPSM82821

    For the webench model,you can change the load current as shown below and it will show the results for PFM mode as well. 

    In the end, the ripple depends on the load current and the amount of output capacitors you have. The maximum limit I mentioned earlier was for the output capacitors and is mentioned below. 

    You can use 2x10uF or 1x 22uF output capacitor for an optimal operation of the device.

    Thanks!

    Best regards

    Sneha