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UCC14140-Q1: Rlim/RDR selection and thermal issues

Ishaan Bhimani
Prodigy 60 points
Part Number: UCC14140-Q1
Other Parts Discussed in Thread: UCC14141EVM-068

Power Management Forum

E2E Thread Title – UCC14140-Q1: Rlim/RDR selection and thermal issues

I am using the UCC14140-Q1 with dual output. The VDD-VEE voltage is 20V, and the COM-VEE voltage is 5V. I noticed that the way the datasheet solves for Rlim conflicts with the method from the UCC1414x-Q1_Calculator_V7.xlsx tool that TI provides. Can you please confirm my selections?

System parameters are below:

Vin: 12V

Cin: 20.1uF (as recommended)

VDD-VEE: 20V

COM-VEE: 5V

Qgtot: 1135nC

Switching Frequency of Gate Driver Load: 20kHz

Quiescent current of gate driver from VDD-COM: 4.95mA

Quiescent current of gate driver from COM-VEE: 6.21mA

Quiescent current of other load on VDD-COM: 0mA

Quiescent current of other load on COM-VEE: 10mA

Bottom feedback resistor between FBVDD and VEE: 10kΩ

Bottom feedback resistor between FBVEE and VEE: 10kΩ

Desired AC gate-switching ripple percentage between VDD and COM: 5%

Max component tolerance of Cout2 and Cout3: +/- 10%

Max Avg Power capability based on provided SOA and Tamb: 1.5W

Max transient power capability based on provide SOA and Tamb: 2.20

 

Using my own calculations AND the provided component selection tool, I found that
K23 = 2.69

Due to some layout and design constraints, we have opted to select a Cout1b of 0uF, although we have included the recommend Cout1 of 10.1uF near the DC/DC module. Further, we are constrained to a minimum Cout2 of 30uF, and have thus chosen a Cout3 of 90uF.

 

Moving on to the Rlim requirements. I followed the procedure outlined in pages 35-37 of the datasheet for both the single and RDR configurations.

 

Single configuration:

The datasheet indicates that the Rlim in the single-resistor configuration should be the minimum of the results from Equations 10, 11, and 12.

Equation 10:
 

Equation 11:

 

Equation 12:

 

The discrepancies I have found are as follows:

  • Equation 10: for the (1-ΔCout3), the spreadsheet instead uses (1+ΔCout3)
  • Equation 11: for the (1-ΔCout2), the spreadsheet instead uses (1+ΔCout2)
  • Equation 12: the spreadsheet assumes ΔICOM_SINK is not 0, but in my case, ICOM_VEE>IVDD_COM, so I used a ΔICOM_SINK of 0 (see Equation 11).

In the single resistance case, Equation 12 is the lowest value in both the provided spreadsheet and my calculations, but the aforementioned discrepancy changes the result from 924 Ω (spreadsheet) to 265Ω (my calculations).

In the RDR case, Equation 10 is used to identify RLim1, so the discrepancy in the spreadsheet affects this value as well.

Solving for Rlim2, I used Equation 14:

The discrepancies in Equations 10 and 12 directly affect this calculation. Furthermore, the spreadsheet yields a value for Rlim2 that is significantly higher than that of Rlim1. However, the datasheet indicates that Rlim1 should be significantly higher than Rlim2.

Can you please confirm the Rlim values that I have chosen?

In the single Rlim case, I have Rlim = 266Ω

In the RDR case, I have Rlim1 = 1326Ω, Rlim2 = 299Ω.

 

Additionally, I have tried to integrate this DC/DC module into our system using the RDR configuration that I calculated, and I am seeing a very high temperature rise of the module (measured using a thermocouple on the top of the package). Using the thermal resistances provided in the datasheet, I estimate that the package case should only get to about 48°C while switching. However, the case reached over 110°C before I shut down the test, and the temperature was still rising. Further, it seems the steady-state temperature when the gate driver is NOT switching is about 70°C, which is much higher than expected. I am in the process of confirming the quiescent current loading the DC/DC module when the gate driver is not switching, but is there anything else that might cause such high temperature rise? Is it connected to the Rlim and Cout component selection?

Thanks in advance for your help!

P.S. I have attached my personal spreadsheet that I used to follow the datasheet calculation procedures for your reference.

7181.v2.2 GD PSU calculation spreadsheet.xlsx

  • 0
    TI__Mastermind 32775 points

    Ishaan,

    I haven't gone through all your Excel calculations but a few comments I have:

    1. For the single RLIM case, the calculated value of RLIM=266Ω is low. The temperature IC temperature rise would greatly benefit from the RDR configuration.
    2. You mentioned not using Cout1b due to some layout constraints. Cout1b may seem like you are adding an additional capacitor but following the guidelines in the Excel calculator will show that the total required capacitance will actually be less when using Cout1b compared to without.
    3. Refer to section 5.11 in the UCC14141EVM-068 User Guide here and you can compare to the thermal performance I am measuring. The UCC14141EVM-068 is also not taking advantage of the RDR configuration for RLIM. Your measured case temperature seems much to high but I would need to review your schematic, PCB layout and have a description of the electrical test conditions that are resulting in such a high case temperature?

    Regards,

    Steve

  • 0 in reply to Steven Mappus1
    Prodigy 60 points

    Hi Steve,

    Thanks for the quick reply.

    1. This test was run with the RDR configuration with Rlim1 = 1.21kOhm and Rlim2 = 287Ohm
    2. We are using this board to mate with another board that has the gate driver on it. The other board already has high capacitance on the VDD-COM and COM-VEE rails, so we are constrained by those capacitances. This is the reason for Cout2 being 30uF and the Cout3 of 90uF is calculated using K23 ratio from the spreadsheet. This is also the reason we cannot add a Cout1b by the gate driver. I understand that Cout1b actually reduces the necessary Cout2 and Cout3, but since ours are very high, I am hoping that we won't need a Cout1b. Does that sound okay to you?
    3. Schematic and PCB layout of the board are shown below.

    Note: There are 2 of these DC/DC modules on this board, isolated from each other. The schematics are identical and the layout is very similar, and we are seeing similar issues on both sides.

    Test conditions:

    We are using these DC/DC modules as gate drive power supplies for our gate drivers that drive SiC MOSFETs on an motor. We tested these modules by connecting them to the MOSFETs, which are connected to the stator of our motor. The bus voltage across the half-bridge of MOSFETs was 750V, but there was no load on the motor, so the current draw from the HV power supply was very low (0.27A). We were measuring the temperature of the case with Type K thermocouples glued onto the casing, and we were driving the MOSFETs test for about 15 minutes. A temperature plot vs time is below.

    Please let me know if there is any other information that you think could be helpful.

    Thanks!

  • 0 in reply to Ishaan Bhimani
    TI__Mastermind 32775 points

    Regardless of the load on the motor, what is the total load seen by the UCC14140? This is the total load of the gate driver bias, any additional bias and the SiC switching?

    Also, for your PCB layout, I would recommend to follow closely the guidelines published in section 9.5 here. Since you already have a completed PCB, you can compare between what is recommended and what you already designed. Also, you have copper underneath the UCC14140 (not recommended) which is rated for 3kV. What is your isolation requirement? Schematics look good but it would be good if you could place some VEE-COM capacitance on the bias card. Right now you have all the VDD-COM capacitance (30μF) on the driver card.

    Regards,

    Steve

  • 0 in reply to Steven Mappus1
    Prodigy 60 points

    Hi Steve,

    I dug into the quiescent current, and I realized that I made a mistake when estimating them. The following are direct measurements.

    On the low-side:
    VDD-COM current: 10.44mA
    COM-VEE current: 12.69mA

    On the high-side:
    VDD-COM current: 10.43mA
    COM-VEE current: 5.54mA

    Additionally, the power draw from SiC switching would add Qg*fsw*[VDD-VEE] = 1135nC * 20kHz * 20V = 0.454W


    VDD-COM = 15V
    COM-VEE = 5V


    In total:
    LS:

    0.454W + 15V*10.44mA + 5V * 12.69mA = 0.674W

    HS:
    0.454W + 15V*10.43mA + 5V * 5.54mA = 0.638W

    I am recalculating the Rlim values for the LS and HS. Can you please confirm the signs of the ΔCout2 and ΔCout3 in the equations 10, 11, and 12? The spreadsheet conflicts with the datasheet, but in the HS case where the COM-VEE current is lower than VDD-COM current, the datasheet method gives me an unreasonable answer (divide by 0 error) whereas the TI provided spreadsheet gives me a feasible answer.

    Regarding isolation:

    We may make a future iteration on this board, and in that case, we will do our best to follow the keep-out as indicated in the datasheet. Right now, our isolation spec is 2.4kV.

    Thanks for your continued help!

  • 0 in reply to Ishaan Bhimani
    TI__Mastermind 32775 points

    Equations in the data sheet are correct. Below is the RLIM design guidance for the case that a single RLIM resistor is used and the RDR case. Use the Excel calculator spreadsheet and you will be good.

    Steve

  • 0 in reply to Steven Mappus1
    Prodigy 60 points

    Hi Steve,

    The spreadsheet calculator conflicts with this. Specifically:

    In the denominator of the R_lim_max_H equation, there are two terms that use (1-ΔCout3), and in the denominator of the R_Lim_Max_L1 equation, there are two terms that use (1-ΔCout2). However, the spreadsheet uses an addition instead of a subtraction.

    Here is the formula that the spreadsheet uses for R_lim_max_H:

    And the intermediate value ILIM_UP, where the sign discrepancy is:

    Here is the formula that the spreadsheet uses for R_lim_max_L1:

    And the intermediate value ILIM_DN, where the sign discrepancy is

    ...

    I have a feeling that the spreadsheet is doing it correctly, but I want to make sure so that I don't run into any problem down the line. Thanks for bearing with me and helping me sort this out.

    P.S. I think R_lim_max_L1 in the design guidance you sent should have an additional -R_lim_int term:

  • 0 in reply to Ishaan Bhimani
    TI__Mastermind 32775 points

    Yes....good catch - thanks!

  • 0 in reply to Steven Mappus1
    Prodigy 60 points

    Can you please confirm what ΔCout2 and ΔCout3 are? I assumed that they were the decimal representation of the percent tolerance of Cout2 and Cout3, i.e. if Cout2 has 10% tolerance, then ΔCout2 is 0.1.

    In my case, the tolerance for Cout2 and Cout3 are both 10%. You can see that according to Equation 10:

    If ΔCout2 and ΔCout3 are equivalent, then (1-ΔCoutx) factors out, and the term in the brackets goes to 0. Further, if ΔI_com_source is 0, in the case where Icom-vee < Ivdd-com (which is the case for the high-side module), then the denominator is 0. This is the problem that I am running into. How would I size R_lim_max_H then? This is necessary for the RDR configuration.

  • 0 in reply to Ishaan Bhimani
    TI__Mastermind 32775 points

    Hi,

    Use the Excel tool calculator. 

    Steve

  • 0 in reply to Steven Mappus1
    Prodigy 60 points

    Hi Steve,
    Thanks for your help thus far. I recalculated values using both my hand calculations and the Excel tool calculator. When I turn on the device, it quickly drops the output voltage to 0. This is on the low-side DC/DC module, meaning the measured VDD-COM quiescent current is 10.44mA and the COM-VEE quiescent current is 12.69mA. I tried the resistance values from my hand calculations (R1 = 6.19kOhm, R2 = 237Ohm) and from the Excel tool (Rlim = 4.64kOhm, R2 = 287 Ohm).


    In both cases, the DC/DC module immediately turned off. Do you know what would cause this?
    One thing that I notice that could potentially be a problem is the output capacitance. As I mentioned before, the board with the DC/DC modules mates with a board that has the gate drivers on it. We are following the ratio for Cout2/Cout3 (2.93) given in the spreadsheet, but we have significantly oversized values. The suggested Cout2 from the spreadsheet is 1.513uF, and we have 30uF and a Cout3 of 92.2uF. Do you know what the maximum capacitance loading for this DC/DC module is?


    We are also loading the COM-VEE rail with an LDO that steps the voltage from -5V to -4V, and runs some sensing circuits off of it. As I've mentioned, I have measured the quiescent current, so I believe the calculations took this into account, but do you think that the LDO could affect the stability of the DC/DC module?
    I have included some screenshots of our schematic for visual aide.


    Figure 1: DC/DC Module with -4V Regulator loading


    Figure 2: LS Gate Driver Schematic

  • 0 in reply to Ishaan Bhimani
    TI__Mastermind 32775 points

    Do you have any instantaneous start-up waveforms? How about VIN, RLIM, VDD-VEE, COM-VEE captured as single event showing the outputs trying to start and then shutting down? A common cause of start-up problems is output UVLO and/or OVP protection. In section 5.9 of the UCC14141EVM-068 EVM User Guide, I intentionally invoked output UVLO and OVP faults to show what the protection waveforms look like when the UCC14141 doesn't start-up. 

    Regards,

    Steve

  • 0 in reply to Steven Mappus1
    Prodigy 60 points

    Hi Steve,

    I took some start-up waveforms, and they were very insightful. Thank you! They are shown below. I performed this on a system with reduced capacitance. For this test, Cout2 is 10uF and Cout3 is 32.2uF (as opposed to Cout2 = 30uF, Cout3 = 92.2uF from before), and I used values based on the TI provided excel tool.

    The waveforms show the following:

    Channel 1

    VDD-COM

    Channel 2

    VEE-COM

    Channel 3

    Voltage across Rlim (negative side on COM)

    Channel 4 (isolated probe)

    nPG

    Capture 1. The gate driver was turning off immediately after startup. I see in this waveform that nPG never goes low, and that the VEE-COM voltage never reaches the desired -5V. Based on the reference you sent, this looks like an output UVLO issue caused by VEE-COM being loaded too much on startup.

    Capture 2. Trying to work around the issue, I disabled the LDO that runs the temperature sensing circuit. Therefore, the only load on VEE-COM is from the gate driver quiescent current.

    I see now that the regulator reaches the desired voltage and nPG goes down.However, it faults out soon after. I see that the voltage VEE-COM goes down to -5.6V, which is over 110% of the desired -5V. This leads me to believe this is an output OVLO protection. I also see that the voltage across RLIM is negative, but it does not go back to positive until after the fault. This makes me think that the Rlim values were not sized correctly, since I changed the steady-state load on VEE-COM.

    Capture 3. I recalculated the values based on this new load, and the regulator seems to be working!

    However, I will obviously need to be able to apply the load after startup. I am hoping that using the values calculated for the actual steady-state load, I can get the regulator to work by applying the load once nPG goes low. I am working on a way to be able to apply the load after nPG goes low, but it is possible we will just have to delay the enable of the VEE-COM load. I saw the following in the datasheet:

    The datasheet recommends waiting 35ms before loading. However, you can see in capture 2 that the regulator faults after about 15ms. My follow-up questions are as follows:

    1. Do you know why the regulator is faulting out quicker than the recommended 35ms?

    2. Does the logic I stated above make sense? Is there anything that I missed that might help me understand these phenomena?

    Thank you so much!

  • 0 in reply to Ishaan Bhimani
    TI__Mastermind 32775 points

    Makes sense. The 35ms timeout is for UV output faults. We allow up to 35ms for the output voltages to reach regulation and if not achieved by 35ms, the converter commences with output UV fault. For output OV fault, the converter processes this fault immediately. Output OV is not limited to 35ms and can happen at any time. If output OV is detected at startup this can happen at various points in time depending on output cap size, load conditions, etc.

    Also, recommend to not attach your scope probe GND lead to the output capacitor midpoint (COM). COM is only a virtual floating GND but the real output GND is VEE and this is where you attach your scope probe GND leads (you will notice the EVM has PCB test points for inserting tip and barrel scope probes into the PCB with VEE as the GND reference. To see the scope produce VEE-COM=-5V, I use the math function of the scope to invert the signal and display VEE-COM=-(COM-VEE). To display VDD-COM, I use the math function to get VDD-COM=(VDD-VEE)-(COM-VEE)

    Steve

  • 0 in reply to Steven Mappus1
    Prodigy 60 points

    Hi Steve,

    Using my original capacitance values (Cout2 = 30uF, Cout3 = 92.2uF) and having disconnected the LDO that loads the -5V rail, I am able to see the regulator power up into a steady state. However, as soon as I connect power to the LDO, the regulator faults. I calculated the Rlim values based off of the measured load current and used the TI Excel tool, so I think the values are correct. Furthermore, I see a spike in the VDD-COM voltage, and the fault looks like an output OVP protection fault, since the VDD-COM voltage gets up to 16.6, just out of the 110% range of 15V. I am wondering if this is because connecting the LDO provides too much of a transient on the load, but if it can make it past the transient (or slow it down), then the regulator might continue to work. Do you know what's causing it to spike the VDD-COM voltage, and what I can do to prevent it?

  • 0 in reply to Ishaan Bhimani
    TI__Mastermind 32775 points

    You need to have a good understanding of the dynamic nature of the load. It is best if possible, to not be starting up into a dynamic load. Sounds like you now have a much better working knowledge of the UCC14141 and the different fault protections. I am going to close this thread because it is getting quite long. Please continue to use E2E and open a new thread if additional support is needed. Please lick resolve if this thread helped solve your issue?

    Regards,

    Steve