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LP2951-N: Trying to figure out the correct max Tj

Tim Hogue1
Prodigy 20 points
Part Number: LP2951-N
Other Parts Discussed in Thread: LP2951

I would like to operate the LP2951ACSD/NOPB in an environment where Ta=125C, input voltage of 10-30Vdc, output voltage set to 10V using 732K between Vout and FB pin and 100K between FB pin and ground.  My load current can be up to 15mA, which I calculate will cause a rise in junction temperature Tj of either 8C if using Rθ(JB)=23.3 or a rise in Tj of 15C if using RθJA=43.3.  The part package is WSON-8(NGT) and will be mounted to 1.6mm thick PCB with 8 x .254mm thermal vias from power pad into an internal 1oz copper ground plane that is 12 x 38mm or 456mm^2.

The first question is which thermal metric, Rθ(JB)=23.3 or RθJA=43.3, would be closer to reality for my application?

The second question is what is the actual maximum Tj temp for this part, 125C or 150C?  On page 5 of the datasheet it shows that LP2950AC-XX, LP2950C-XX and LP2951AC-XX, LP2951C-XX parts are only good up to 125C whereas the LP2951 parts are good up to 150C.  Which is it for LP2951ACSD/NOPB?

  • 0
    TI__Mastermind 44385 points

    Hi Tim,

    Sorry for the delay. I will get back to you tomorrow about this. 

    Regards,

    Nick

  • 0
    TI__Mastermind 44385 points

    Hi Tim,

    Is the 12x38mm copper ground plane the only ground copper that the device is connected to? Is there any additional copper on the external layers? The RθJA is simulated using the JEDEC High-k board layout, which is at least 76mmx114mm (I don't have the actual board dimensions that we use on hand) and has a full internal copper plane of this size, and has more copper on the bottom layer as well, so as far as I can tell your layout will have lesser thermal performance than the 43.3C/W in the datasheet. If you can afford any more room for ground copper, top and bottom layer copper is the most effective at getting heat off the board since it has contact with the ambient air. 

    Something to consider to help improve thermal performance is that it is better to use more, smaller vias than it is to use less, larger vias. If your board manufacturer can do less than .254mm hole size, it would be better to use the minimum size and pack more of them in. 

    I am still trying to find the information for your second question. This is a legacy device from National Semiconductor, so our documentation is a bit limited. 

    Regards,

    Nick

  • 0 in reply to Nick Butts
    Prodigy 20 points

    Hi Nick,

    Yes, there is actually an external copper ground plane on the same layer that the regulator(s) are mounted to that I did not include.  It is the same 12x38mm size, but it has some additional components such as four 1206 caps, four 0603 caps, four 0603 resistors, and an additional LP2951 regulator mounted to it.  I did not include mentioning the 2nd regulator because its load requirements are much less in comparison.

    I understand what you're saying in regards to increased thermal via count and improved thermal performance of the copper-to-air interface vs internal layer.  I will try to include your suggestions in the next layout revision.

    I still need an answer to 2nd question.

    Thank you,

    Tim

  • 0 in reply to Tim Hogue1
    TI__Mastermind 44385 points

    Hi Tim,

    Got it. I'm waiting on a response for the 2nd question. I'll ping them again.

    Regards,

    Nick

  • 0 in reply to Tim Hogue1
    TI__Mastermind 44385 points

    Hi Tim,

    Sorry for the delay. The device in question is a 125C device. 

    Regards,

    Nick