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LM74502: Power on Behavior

Michael Chang68
Prodigy 235 points
Part Number: LM74502

Hello,

I am using LM74502 in our design as input reverse protection. Below is part of the schematics. In my test, 24V DC is the input voltage, there is no load connected to the output.

I found a strange behavior on output voltage when powering up. There is a small bump on the output voltage before the output power is fully brought up, as shown in the graph below. "SHDN" signal is connected to EN/UVLO pin of LM74502. From the graph, it shows "SHDN" signal becomes HIGH more than 400ms after that bump on the output voltage.

Then, I checked VS, which is the input voltage in our design, and VCAP. It shows that the voltage between VCAP and VS also becomes valid more than 400ms after that bump on output voltage, as shown in the graph below.

I also measured voltages on GATE and SRC pin of LM74502 as shown below. According to V(GS), the external NMOS should be turned on at our expected time, more than 400ms after the bump. In fact, that bump appears on GATE and SRC pin as well.

Based on these test results, I believe the charge pump and gate driver of LM74502 work as designed. The bump on output voltage, GATE and SRC pin seems the result of coupling. Have you discovered this phenomenon in other circuits with LM74502 before? Is it possible that the coupling path is inside those external NMOS? Is there a way to solve this kind of problem?

Thank you!

  • 0
    TI__Guru 57737 points

    Hi Michael, 

    Thanks for reaching out to us. We have not seen this behavior with LM74502-Q1 before. The GATE and SRC are connected together internally when GATE is turned OFF. So, any voltage on SRC can also be seen on the GATE pin. 

    As you mentioned, this behavior during Vin ramp up could be due to the coupling from the drain to source of the FETs Q2, Q3, Q4 and Q5 mostly due to the Cds of the FETs. To verify this, can you remove the  Q2, Q3, Q4 and Q5  FETs from your board and do the same test to see if there is coupling on SRC pins.

  • 0 in reply to Praveen GD
    Prodigy 235 points

    Thanks Praveen!

    I will do that test and let you know the result.

  • 0 in reply to Michael Chang68
    TI__Guru 57737 points

    Sure Michael. We will wait for your test results

  • 0 in reply to Praveen GD
    Prodigy 235 points

    Hi Praveen,

    I re-measured those signals.

    When there is no load on the output connector, the amplitude of the pulse on VOUT is around 20V. In the graph below, channel 3 is SHDN (EN/UVLO) signal, not SRC.

    Then, I removed three out of four NMOS (Q3, Q4 and Q5 in schematics) between VIN and LM74502 and measure VIN1_P1. There is still bump in the output power, but the amplitude is reduced from around 20V to 13.8V. Though the amplitude is reduced, but it is not in proportion with the change of NMOS. The number of NMOS is reduced by 75%, but the amplitude of this voltage pulse is only reduced by less than 50%.

    Finally, I removed all of the four NMOS between VIN and LM74502. The test result is below. There is no bump on VOUT before gate driver begins to work. But VOUT reaches about 28V (VIN is 24V) when the gate driver begins to work and then gradually reduce so around 10V. In the second graph below, it shows that the VOUT and the voltage on SRC pin are the same, probably VOUT is following SRC through the body diode of the NMOS at this time.

    Why the voltage on SRC pin behave like this? When the gate drive begins to work and make the voltage on GATE pin higher than VIN, I expect SRC pin should be separated from GATE pin, but in the graph it seems that SRC is still connected to GATE when GATE pin is driven to around 35V, after that SRC drops to around 10V. This makes the V(GS) become 25V, which is much higher than that in the spec.

  • 0 in reply to Michael Chang68
    TI__Guru 57737 points

    Hi Michael, 

    As expected, the coupling from the drain to source of the FETs Q2, Q3, Q4 and Q5 is the root cause of the glitch on VOUT when VIN is ramped up.

    Regarding the second question where SRC voltage is coupled to GATE, can you elaborate on the test condition ? Are the FETs  Q2, Q3, Q4 and Q5 disconnected ?

  • 0 in reply to Praveen GD
    Prodigy 235 points

    Hi Praveen,

    In the test when I said "I removed all of the four NMOS between VIN and LM74502", Q2, Q3, Q4 and Q5 are removed from the board, but Q10, Q19, Q20 and Q21 are still on the board.

    The measured signals "GATE" and "SRC" are measured on the pins of LM74502 (U40). "V(OUT9)" is measured ate VIN1_P1 in the schematic. No load is connected on the output side.

  • 0 in reply to Michael Chang68
    TI__Guru 57737 points

    Hi Michael,

    Regarding the coupling of Gate when the FETs Q2, Q3, Q4 and Q5  are removed, we will verify this behavior on EVM and get back to you. 

    Meanwhile can you add some load (100kΩ to GND or 10kΩ to GND) at the output to see if the VOUT and SRC voltage discharges. This will give us an idea on the strength of decoupling current.  

  • 0 in reply to Praveen GD
    Prodigy 235 points

    Hi Praveen,

    I tested with a load (100k Ohm to GND) at the output. Now the voltage at VOUT and SOURCE doesn't go above 25V during powering up, instead, they keep at around 6V. GATE signal is still driven to above 30V when EN/UVLO becomes HIGH (known from previous test).

    Below is the graph when 100k Ohm load is at the output. Since now the V(GS) has reached around 25V and the max V(GS) of the NMOS (SiRA80DP) is +20/-16V, I suspect the remaining four NMOS have been killed already.

    I can understand the GATE is driven to HIGH because all the three conditions are achieved according to section 8.3.3 of LM74502's datasheet. But I am wondering where does the voltage on SRC come from.

  • 0 in reply to Michael Chang68
    TI__Guru 57737 points

    Hi Michael,

    Your test shows that the leakage current strength in the order of 10's of uA. 

    When tested on EVM with the following test conditions and we do not see any voltage on SRC or Vout.

    • Q3 FET removed (schematic below for reference),
    • Q4 populated 
    • 12V Vin applied
    • EN pulled high 

     Please find the waveform capture below.

    Looks like the leakage in your case is from Q10, Q19, Q20 and Q21 FETs gate-source. To verify this, you can remove these FETs and check the SRC and Output voltages. After removing all the 8 FETs in your board, there should be no voltage rise on  the SRC and VOUT which indicates there is no leakage or coupling of gate voltage through the internal circuits of the controller to SRC and Vout.