TPS65296: VDD_EN and VDDQ_EN control

Sirui Zhu

Intellectual 2090 points

Part Number: TPS65296

Hi team,

Could you please help advice how to to control VDD_EN and VDDQ_EN without a MCU or GPIO? My guess is connecting PVIN and VDD_EN together and add RC delay to power up the PMIC. However there is a pic in datasheet says VDD_EN need to deassert befor VDD1 goes down. Do you have any suggestion on the enable pin control?

Sirui

over 2 years ago

0 Zixu Wang over 2 years ago

TI__Expert 8100 points

Hi Sirui,

I will check and give you reply next week!

BRs

Zixu

0 Sirui Zhu over 2 years ago in reply to Zixu Wang

TI__Intellectual 2090 points

Hi Zixu,

Looking forward for your reply!

Sirui

0 Yuchang Zhang over 2 years ago in reply to Sirui Zhu

TI__Mastermind 18510 points

Sirui,

The picture shown in DS means VDD1 and VDD2 power on/off timing internally controlled by VDD_EN signal, after VDD_EN disserted, VDD2 will drop firstly and then VDD1 will drop after T4 delay (both are controlled by internal logic). but above timing is based on EN drop after PVIN drop, if PVIN drop faster than VDD_EN, that may cause different timing. So suggest VDD_EN disserted before PVIN drop to < UVLO if customer's application would following the timing shown in picture.

Yuchang

0 Sirui Zhu over 2 years ago in reply to Yuchang Zhang

TI__Intellectual 2090 points

Hi Yuchang,

Thanks for your reply. Understand that VDD_EN sequencing. What I'm looking for is a method to comply with both power-on and off sequencing, without using GPIO. Could you please suggest some way like RC delay circuit?

Sirui

0 Yuchang Zhang over 2 years ago in reply to Sirui Zhu

TI__Mastermind 18510 points

Sirui,

Divided from VIN or VCC should be ok, just recommend to EN on after PVIN/VCC ready and off after PVIN/VCC off, such as you may set VIN higher than 6V for VDD_EN asserted threshold, and VDD_EN could be off before PVIN/VCC drop off.

Yuchang

Power management

Power management forum

TPS65296: VDD_EN and VDDQ_EN control