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UCC28180: phase margin of current loop

Francis
Prodigy 90 points
Part Number: UCC28180

Good morning, I'm building a PFC CCM with your UCC28180 integrated circuit.

These are the rough specifications

Vin = 180-264V
Vout = 400V
Iout = 2 A

fsw = 110 kHz

L = 250 uH (with 40% ripple peak to peak)

I'm sizing the feedback systems with your excel calculator.

In sizing the current feedback I am finding phase margins of 16-28°.
I wanted to understand if it is normal to find such low phase margin values.

I am attaching both the values ​​set in the excel file for Vin_max = 264V  and Vin_min = 180V and the corresponding graphs

 Until now I have designed only the control of the voltage loops of buck converters where the phase margin is acceptable only if it is greater than approximately 60°.

  • 0
    TI__Mastermind 40120 points

    Hello Francis, 

    The current-loop phase margin for this device does tend to be rather low since there are few effective options to improve it.
    Reducing the ICOMP capacitance moves the pole higher which increases the crossover frequency and allows a higher margin, but the averaging of the ripple current is less effective and could have other detrimental effects. 

    The UCC28180 is optimized to operate over the so-called "universal line" range of 85~265Vac.  I think the low margin generally happens when the device is used for high-line-only applications where the maximum input current happens at a high input voltage.

    Regards,
    Ulrich