CSD18511KCS: Can the high side MOS maintain continuous output？

Liujun,

Apologies for the delay in response due to the holiday here in the USA.

In answer to your question, this depends on the floating supply for the HS FET.  In a bootstrap circuit usually used, the floating supply is held by a capacitor that needs off time to recharge (it’s basically a very basic version of a switched capacitor circuit).  But in the image you provided, the floating supply is undefined.  So it’s not possible to say whether the HS can be left on indefinitely.  From a FET standpoint, keeping the HS on forever and LS off forever shouldn’t be an issue.  Obviously, you need to avoid having both on at the same time to avoid shoot-through/short circuit.

Thanks

Chris

Hello Liujun,

Thanks again for your interest in TI FETs. In order to keep the high side FET turned on, you must apply a voltage at the gate that is at least 4.5V greater than the DC input voltage connected to the drain. When the FET is on, the drain and source voltages are approximately equal so VGS = Vgate - Vdrain and must be > 4.5V. Please note, leaving the HS on continuously will saturate the inductor which could cause excess current flow through the FET and damage it.

Best Regards,

John Wallace

TI FET applications

Hi Liujun,

I believe you are correct but you need to make sure that the output of the opto-isolator drives the gate to at least 4.5V greater than DC voltage applied to the drain of the high side FET to ensure it remains on.

Thanks,

John

Hi Liujun,

In general, all MOSFET datasheets specify the minimum value of VGS where Rds(on) is tested and guaranteed. This is true for all TI FETs including the CSD18511KCS datasheet which specs Rds(on) at a minimum VGS = 4.5V. As I explained in my earlier response, when the FET is on the drain and source voltages are approximately equal. For a high side switch where the source is not connected to GND, the gate voltage must be pulled up higher than the drain voltage (because Vdrain ≈ Vsource) by the minimum VGS value where Rds(on) is specified in the datasheet. The voltage can be higher (all the way up to the abs max value specified in the datasheet which is 20V for the CSD18511KCS). The FET is turned on by applying a voltage between gate and source not between gate and drain.

Thanks,

John

Hi Liujun,

In your circuit diagram the FET will be operating in the saturation region (Vds > Vgs - Vth). This is also known as linear mode operation. I created the attached simple TINA-TI simulation to estimate the DC operating conditions for your circuit. With a typical device, VO = 9.82V, VGS = 2.18V, VDS = 8.18V and ID = 98mA. In order to guarantee that the FET is on, VGS must be at least 4.5V. If the battery voltage is say 23V, then the FET will be fully turned on: VO = 18V, VGS = 5V, VDS = 498μV and ID = 179.5mA.

Best Regards,

John

CSD18511KCS_Bias.TSC

Hi Liujun,

The CSD18511KCS has a absolute maximum VDS rating of 40V. You cannot apply 700V to the drain of the FET. It will be destroyed and likely will expose the battery to 700V causing catastrophic failure. You will need a FET with a breakdown voltage > 700V.

Thanks,

John