UCC5350-Q1: Error in simulation

Hi Anand,

This Vds spike is an important problem to solve in a power supply design, as it will otherwise damage you switches or force you to use more expensive high voltage switches than required. The V= L * dI/dt. Adding a gate drive resistor would increasing switching dt, and reduce the dI/dt. You really need to increase dt a lot to slow the gate charge for a small Cgate, and this also increase switching losses.

A solution I prefer is to add a snubber to the supply rail. This is more to stop the switch node from ringing back and forth, but it does reduce the spike amplitude a little. I attached an TINA-TI example of how to optimize the snubber resistor value for a given power rating.

Another way to guarantee the switches are not subject to overvoltage is to use TVS diodes. This is not a popular solution but they are fool-proof, and allow you to use voltages very near the FET voltage ratings.

Another solution is to use a ground/power plane. This will reduce the inductance a lot, and reduce the under/overshoot. Once you have a low inductance plane, it is a lot easier to add clamping diodes for transient voltages where they appear.

Best regards,

Sean

0474.GateRing3.TSC

P.S., remember that a closed switch is immune to overvoltage. If you see high voltage ringing across two pins that are shorted, you are likely measuring a voltage across a parasitic inductor, not the silicon. 

You don't really want to add the snubber onto the switched node itself. There it will have to charge and discharge to a high voltage every cycle and burn a lot of power.

The most effective snubber is one that is on the local decoupling capacitor. It gets shorted to the switch node when the high side switch closes. This will let you dampen the resonance without the capacitor needing to cycle high voltage. You might need two snubbers: one to snub the drain inductance of the FET package, and one to snub the overall supply inductance from the battery or large decoupling capacitors. They will ring at two different frequencies. 

You are right that the snubber won't clamp the initial peak that much, but you do need to get rid of the resonance too. It can couple into the gate driver and cause damage. It also decreases the usable duty cycle of the PWM.

To get rid of the peak you should try to use TVS clamping diodes. They absorb the first peak, and if the switch node+supply is weIl damped, the voltage will just recover to the right value with minimal ringing. IGBTs have a natural avalanche breakdown that absorbs these peaks (within reason), which is a significant benefit vs. SiC. It might be worth looking at if you can sacrifice switching and conduction losses and are very concerned about overvoltage. Usually, though, The switching loss is the first priority, and you are better off using TVS diode to address this issue.

Note that a power plane will have significantly lower inductance vs. a trace. This increases the resonant frequency to a level where it will be damped better by the low parasitic series resistance, and will therefore lower the peak voltage.

Best regards,

Sean