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LM5143A-Q1: SW node pulse skipping

Part Number: LM5143A-Q1
Other Parts Discussed in Thread: LM5143, PMP23404

Hi,

I am having a problem using the LM5143A-Q1 in interleaved mode where the SW node is pulse skipping every other pulse. My converter operates at 100kHz, but the SW node only switches at 50kHz. Because half the pulses are being missed, the duty cycle on time is double what it should be. This is causing a false overcurrent trip condition. Why would the converter be skipping every other SW node pulse? Incorrect compensation component values? Incorrect inductor DCR current sense values? Incorrect output capacitor ESR? I'm not sure what knobs to adjust to get my regulator to work.

Below is my schematic for this design.

Design criteria:

Vin = 20-56V

Vout = 3.8V

Fsw = 100kHz

Iout max = 50A

Below is a screenshot. Notice the SW node is on for double it's expected on time (should be on for ~0.7us and it's on for ~1.4us). The SW pulses do happen every 100kHz, but only the ones that happen at 50kHz have a useful duty cycle (half of them are only on for ~50ns, which is barely anything).

  • Brandon,

    Please attach the quickstart calculator for this.

    https://www.ti.com/tool/LM5143DESIGN-CALC 

    I believe your compensation is not tuned for this design, especially with your lower switching frequency.

    If you dont have enough phase margin, then the converter is unstable.

    Please double check your compensation with the quickstart, and then also taking a bode plot of the physical board will be critical information.

    Hope this helps,

    -Orlando

  • Hi Orlando,

    I appreciate your feedback! Attached is the quickstart tool filled out. I want to add that the output capacitor ESR can be as high as 22mohm or as low as 10mohm, but there are 6 in parallel so that drops it down to 1.5-4mohms. I am looking into adding ceramics to help knock that down further.

    Is it possible for you to recommend good starting values? I spent some time playing around with the spreadsheet and I feel like what I have now should be stable (although the transient response may not be the fastest!).

    It is a bit difficult for us to look at the gain/phase margin with the actual design in the lab. It'd be easier to start with values that ensure stability and ignore transient response for now.

    Spreadsheet filled out:

     LM5143A-Q1_quickstart_design_tool_filled_out.xlsm

    Brandon

  • Brandon,

    Do you have this at no-load? Or just a resistive load?

    Also can you show SW1 and SW2? 

    Also a separate plot with VCOMP will be useful.

    Thank you,

    -Orlando

  • Orlando,

    I am using an electronic load, so purely resistive.

    Below is an oscope image of SW1, SW2 and VCOMP. A few interesting notes for you:

    When R4 and R12 are 15k, the SW node looks normal, but the overcurrent still trips earlier than 50A. Below is the image. In this case, the load current shown in green is about 38A. I believe the SW node noise is coupling into VCOMP, so I don't think the noise is real.

    When R4 and R12 are 30k, the SW node does not look normal. Below is an image at 30A load. The overcurrent protection hasn't tripped, but SW CH2 is skipping every other pulse and SW CH1 looks normal. 

    Below is the same setup as below, but the overcurrent trips when the load is increased. It looks like both SW CH1 and CH2 are skipping pulses.

    Lastly, below is the VCOMP net on it's own near the trip point using the 30k resistor values.

    Do you know why the SW node would skip for one channel and not the other? Why would changing those resistor values impact the pulse skipping?

  • Brandon,

    What's the inductor part number? Whats the maximum DCR?

    As you reduce the DCR current sense resistance, the current sense AC signal increases, and that could be cause for early current limiting.

    You might be able to try increasing the DCR current sensing capacitor 2x since you reduced the resistance ~2x.

    Also each channel has its own cycle-by-cycle limiting, so ISNS1 and ISNS2can limit each phase current independently.

    Not sure about why larger resistor causes stability issues, could be higher impedance path being more susceptible to noise.

    Does your PCB layout use the same VOUT line for current sensing and for Feedback path? That is not recommended, for future reference feedback should have its own VOUT connection.

    Hope this helps.

    -Orlando

  • Orlando,

    The inductor PN is WURTH 74436410470. The max DCR is 1.44mohm max, typical is 1.31mohm.

    I agree with you on the AC gain increasing and causing the overcurrent to trip earlier than expected.

    I tried increasing the DCR current sensing capacitor by 2 (220nF) and decreasing the DCR current sensing resistor by 2 (15k) and the regulator wasn't stable (I saw pulse skipping again). I then tried 220nF with 7kohm resistors and the device is stable again, but trips a bit early due to the overcurrent condition (about 38A). So it seems like there is something important about the 2:1 ratio between the inductor's inductance/DCR and the RC filter values.

    The PCB layout uses the same VOUT line for current sensing and feedback path. 

    1) Do you think my compensation network is incorrect or needs to be tuned?

    2) Why is it important to use different traces for current sensing and feedback path?

    3) Your reference design for the LM5143 has an inductance/DCR to RC ratio of 1:1, whereas mine needs 2:1. Do you know why I would need more AC signal to make the regulator stable? Is it due to noise? Converter switching frequency? 

    Thanks for the help so far! I think we're converging on the problem.

    Brandon

  • Brandon,

    What reference design are you referring to?

    Actually the device uses current-mode control, the inductor current is part of the control loop. 

    The larger AC signal will definitely affect the stability, and could make it more stable.

    Ultimately a bode plot will show phase margin and if its stable, then you can tune the compensation.

    current sensing is a differential signal and noise sensitive. The current sensing should be differentially routed from the pins to the inductor.

    Using the same VOUT will cause mismatch in the differential routing, and can pickup more noise.

    I also hope you have a dedicate differentially routed current sensing for both inductors, and not using the same VOUT trace for both current sensing signals.\

    Take a look at the EVM and its layout for example, you can see on the purple layer the current sensing and VOUT FB have their own traces.

    https://www.ti.com/tool/LM5143-Q1EVM-2100 

    Hope this helps,

    -Orlando

  • Orlando,

    The reference design i'm referring to is PMP23404 https://www.ti.com/tool/PMP23404?keyMatch=&tisearch=search-everything&usecase=refdesign

    For both channels of my design, i routed the CS and VOUT pins differentially back to the IC. They are not shared.

    One final question for you: The datasheet gives this relationship: L/DCR=RC. It seems like a 3:1 relationship works best for my design (L=4.7u, DCR=1.4m, R=10k, C=100n). Is there an app note or some guidance on how to tune the RC values other than trial and error? The quickstart calculator doesn't have any equations for it nor does it factor their values into the compensation network design. It sure seems like the RC values do matter a lot though for stability!

    Brandon

  • Brandon,

    Ideally 1:1 should be ideal, and that is assumed by the quickstart.

    Not sure why 3:1 is working better for you, might be noise related.

    That reference design has a current sense filter (R13&C41) right after the DCR current sensing, it might be the difference.

    If your design is working and your bode plot is coming out good then  I think your OK.

    Hope this helps,

    -Orlando