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TPS23525:The prevention mechanism inside the TPS23525 works to prevent through-current

Kazunori Hayami
Prodigy 70 points
Part Number: TPS23525


Hello.

We are conducting an experiment on an ORing circuit using the evaluation board TPS23525EVM-815.
Evalation Circuit

With a constant voltage of -40V applied to the A input, we have gradually increased the voltage on the B input to see if there is any through current from the A input to the B input or from the B input to the A input at the switching point. 

When the voltage of the B input is changed slowly, no through-current flows, .

Slow Transient

but when it is changed quickly, it appears that a transient through-current flows momentarily

Fast Transient

Q1 Please explain how the prevention mechanism inside the TPS23525 works to prevent through-current from flowing from the A input to the B input or from the B input to the A input.

Q2 Please explain why a transient feed-through current flows when there is a quick switchover, and how the prevention mechanism mentioned in Q1 works in this case.

  • 0
    TI__Mastermind 41060 points

    Thanks for reaching out to us.

    Please see the below screenshot. This controller ensures that there is no DC reverse current. Therefore, as the voltage difference between the A and B nodes is slowly created, the amplifier is able to block the reverse current flow. However, when the voltage difference slew rate is fast, as the amplifier is not so fast, there will be some reverse current momentarily. After that, the comparator turns off the FET.

  • 0 in reply to Avishek Pal
    Prodigy 70 points

    Thank you for your response.

    I have a further question.

    Q3
    Is it possible to calculate or simulate the maximum instantaneous value of the reverse current that occurs when the slew rate of both A and B inputs is fast? Is there any way to model the comparator/FET response?

    Q4
    I understand that the control we are doing in this ORing circuit is as follows.
    - FET drop voltage becomes larger than 25mV due to current increase, etc.
    - Neg48A/B voltage becomes lower than VEE-25mV
    - The gate voltage rises until the voltage at both ends of the ORingFET reaches 25mV.
    However, based on the schematic in the datasheet , the Neg48A/B voltage is connected to the + input of the op-amp, which would work as follows.
    - The FET drop voltage becomes larger than 25mV due to the increase of current, etc.
    - Neg48A/B voltage becomes lower than VEE-25mV.
    - Gate voltage moves down and FET drop voltage increases.
    Is my understanding wrong? Or is there some omission in the schematic? Please confirm.

  • 0 in reply to Kazunori Hayami
    TI__Mastermind 41060 points

    The amount of reverse current would be 6-mV/MOSFET RDSON. 

    First the GATE is being regulated at 25 mV and then when the voltage drop increases beyond 80 mV the GATE is fully enhanced.

  • 0 in reply to Avishek Pal
    Prodigy 70 points

    We look forward to your response.
    Thank you.

  • 0 in reply to Kazunori Hayami
    TI__Mastermind 41060 points

    The amount of reverse current would be 6-mV/MOSFET RDSON. 

    First the GATE is being regulated at 25 mV and then when the voltage drop increases beyond 80 mV the GATE is fully enhanced.

  • 0 in reply to Avishek Pal
    Prodigy 70 points

    Thank you for your response.
    I have one more question to ask.
    Fast Comp detects when a reverse voltage is applied across the FET terminals and lowers the FET gate to Lo. The threshold for this is typically 6mV.
    I would like to know the worst-case variation in delay time from when the reverse voltage on the FET exceeds 6mV until the FET actually turns off.
    (I measured the delay time with one sample, and it was approximately 600ns.)
    This information is necessary to estimate the worst-case value of the reverse current.
    Thank you in advance for any information you can provide.

  • +1 in reply to Kazunori Hayami
    TI__Mastermind 41060 points

    Maximum would be around 800 ns.