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TPS61022: Adding feed forward capacitor helps to reduce SW node spikes (Damage to IC stopped) but poor load regulation.

Jaimin Patel
Prodigy 50 points
Part Number: TPS61022

We have used TPS61022 to boost 3.3V supply to 5V (2.5A peak, 0.6A typical) in one of our new design.

TPS61022 IC on 4 out of 10 proto boards (1st proto) failed at power on i.e., SW node short found with GND pin. Sometimes, it worked for few power cycle and suddenly found failed. 6 boards were working fine. Input source was 3.3V current limited DC supply during this testing. We are using this power supply to power up one SOM module and as per their recommended design, we have total 8 Qty 47uF (X7R 10V ceramic) in parallel (spread across board) at output (+5V rail).



We have followed proper layout recommendations as well.


From datasheet, we found that feed forward capacitor (C1 in our design) is recommended for >40uF output capacitor design. Then we have added 1.5nF as feed forward capacitor to all our boards and no failure observed till then. 1.5nF value derived from datasheet equation. We had resistor divider value Rupper - 49.9k and Rlower - 6.8k at that time as shown in schematic snip.
But, output voltage was dropped when we mounted SOM module (i.e., applied load). It was almost 4.65V at 400-500mA load current. Output voltage was varying based on load. Can you please explain why this phenomena happening after adding Cff? Note: We have tried different Input sources also (i.e., 6A current limit DC source and our power board 3A capable 3.3V). Also, we have tried PFM and PWM mode (mode pin low and high), seems same result. We are using PWM mode now i.e., mode pin high).

Now, we started playing with C1 (feed forward) value. We tried 1nF to 100pF and found output voltage drop reduced to 4.85V (C1 = 100pF) at same load (400-500mA). This is ok but can be issue if our load current increases based on processor application load.

Now, to reduce impact of feed forward capacitor, we reduced resistor divider value to lower side keeping ratio same. We used Rupper - 8.25k and Rlower - 1.1k with Cff = 100pf as it is. This helped and at same load current (400-500mA). Load regulation was around 2% (5V from 5.08V). Still, it is dropping while increasing load. So not sure, how to select Cff.

Need someone's help to get how to select Cff and to understand phenomena so we can get confidence to finalize design. Or do you suggest any change in design? Your early response would be appreciated.

  • 0
    TI__Genius 12395 points

    Hi Jaimin,

    Thanks for reaching out and the detailed information.

    About your schematic and layout, we have several suggestions,

     1.We recommend to use 22uF not 47uF output capacitors, because the self resonant frequency of 47uF ceramic capacitors is generally close to 1MHz, the TPS61022 switching frequency is also 1MHz. This may increase the output voltage ripple.

    2. Please place the output capacitors as close as VOUT and GND pin of the IC, this is the most important thing for the IC, there is still large clearance in the present layout, and this is also the reason of the damage, because large clearance will introduce large parasitic inductance, and then cause high spike.

    3. We recommend to add a ~50ohm resistors series with the feedforward cap (C1), which can reduce the possible noise at FB pin. This is helpful to the load regulation issue.

    Jaimin Patel said:
    From datasheet, we found that feed forward capacitor (C1 in our design) is recommended for >40uF output capacitor design

    4.The 40uF here is the effective capacitance not nominal capacitance. You can use the TPS61022 calculation tool in ti.com to check the loop stability, so that you can select the proper feed-forward cap.

    https://www.ti.com/product/TPS61022?keyMatch=TPS61022&tisearch=search-everything&usecase=GPN-ALT

    Let me know if you have more questions.

    Regards,

    Nathan

  • 0 in reply to Nathan Ding
    Prodigy 50 points

    Thanks Nathan,

    We are in process of validating these suggestions on board. I will update you once done.

  • 0 in reply to Jaimin Patel
    TI__Genius 12395 points

    Fine, Jaimin. Waiting for your feedback.

    Regards,

    Nathan

  • 0 in reply to Nathan Ding
    Prodigy 50 points

    Same observation with below value.

    Changed all output capacitor to 22uF instead 47uF (i.e., 22uF *8 + 4.7uF *4 + 10uF = 206uF, Effective capacitance at 5V = 206uF * 0.55 = 115uF).
    Capacitance value is higher than required 23uF as per calculations.
    Resistor Divider - 49.9k (upper) & 6.8k (lower), Cff = 470pF (calculated from that calculator excel) + 47Ω in series, IC in PWM mode.

    Output voltage varies w.r.t. load - approx. 4.75V @ 800mA load. 

    One weird observation is at 100-200mA load voltage output ripple increases to 150-200mV (little unstable) and at higher than ~300mA load, that ripple goes down significantly.

    Could this be regard to SRF of capacitor?

    47uF Capacitor SRF:

    22uF Capacitor SRF:

    Please suggest your thought? Should we change output cap to 10uF?

    Now, I am trying to reduce resistor divider value so Cff impact can be minimized.

  • 0 in reply to Jaimin Patel
    TI__Genius 12395 points

    Hi Jaimin,

    Could you please share the waveforms in this unstable condition? Like VIN, VOUT, SW waveforms, and inductor current if possible. Thanks.

    Jaimin Patel said:
    One weird observation is at 100-200mA load voltage output ripple increases to 150-200mV (little unstable) and at higher than ~300mA load, that ripple goes down significantly.

    Regards,

    Nathan

  • 0 in reply to Nathan Ding
    Prodigy 50 points

    When I added capacitor much near to U1 IC with same configuration above (output capacitor to 22uF instead 47uF (i.e., 22uF *8 + 4.7uF *4 + 10uF = 206uF, Effective capacitance at 5V = 206uF * 0.55 = 115uF).
    Resistor Divider - 49.9k (upper) & 6.8k (lower), Cff = 470pF (calculated from that calculator excel) + 47Ω in series, IC in PWM mode.

    The problem of higher ripple moved at 0.8-0.9Amp load. At 0.6A load, output voltage is 4.96V (<20mV ripple), At 0.8 & 0.9A load output voltage reduced to 4.84V with higher ripple around 200mV and at 1Amp output voltage is 4.95V with 20-30mV ripple (stable).

    Here is waveform when high ripple. Yellow is Input 3.3V, Green is Output V, blue is SW node pin. Same ripple replicates in Input voltage. We have tried changing input source from our system supply to external DC source (6Amp current limit). Added bulk capacitor at input, too. But same observation.



    Then onwards,
    we have made iteration with same all 22uF output cap (115uF effective total), Resistor divider value reduced to 8.25k + 1.1k, Cff = 3.3nF + 47Ω.
    Supply working well. Ripple <20mV in all load condition. Load regulation is 2-3% for 1A load... We have checked same in two boards and thinking to go ahead with this     config.



  • 0 in reply to Jaimin Patel
    TI__Genius 12395 points

    Hi Jaimin,

    Looks like there is no problem now, let me know if you have more question.

    Regards,

    Nathan