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LM5069: Gate start-up issue

Part Number: LM5069

Hello,

I've an issue with an LM5069 Load Switch on my board.

The problem is that the Load SW is supposed to enable the gate of the N-MOS at some defined point, but unfortunately, it doesn't happen. Instead, I observe a strange behavior at the N-MOS Gate. The LM5069 starts toggling the N-MOS gate at a constant frequency.

Before I continue with the issue, I'll describe my electrical system requirements:

  1. Input voltage range – 9V to 36V. Nominal 12V. This is also an input voltage for the LM5069
  2. Output current (through N-MOS) – 6.7A max
  3. Under Voltage – Low=11.2V, High=11.6V
  4. Over Voltage – Low=36V, High=40V

Below is the schematic of LM5069 on my board:

Details of the elements of the scheme (attached LM5069 design calculator with all relevant parameters):

 LM5069_Design_Calculator_REV_C.xlsx

  1. 10mOhm for RSNS – R175
  2. For desired UV values as described below, I've used following resistors:
    1. R1=19.1Kohm – R416
    2. R2=5.49Kohm – R418
  3. Output capacitance: Cout=150uF+100uF. Total Cout250uF (maximum allowed output capacitance based on LM5069 DS – 350uF)
  4. Selected Hot Swap FET (N-MOS) - DMT6005LPS-13 (Q4). FET parameters (DS attached):
    1. Rds(on)≈5mOhm
    2. Vds=60V
    3. Id=125A
  5. Ctimer=220nF (C579), for Tfault=10.35msec
  6. Rpwr=93.1Kohm (R431) for a 74.5W PLIM
  7. System start-up condition:
    1. Load Turn-on threshold – 6V
    2. Start-up load current – 0.5A

Based on these parameters, it seems that the selected components fit my design requirements.

The layout was based on TI recommendations:

So, I expected to see the following graph:

However, the actual situation is quite different. Instead of rising the Gate pin to 23.6V, the LM5069 starts toggling the Gate pin with a sawtooth signal (with a time period of 870 microseconds) at a UVLO.

   

If I increase the VIN to around 13V, the LM5069 starts to act as expected.

In an attempt to stabilize the operating point, I tried to change both the Ctimer and Rpwr values to increase/decrease the Fault Time and Target PLIM, but these changes had no effect.

Please refer to the attached Design Calculator containing all design parameters (entered in green shaded cells). As mentioned below, the maximum current is around 6.7A, but during startup conditions, the current is below 0.5A at 13V.

  • Thanks for reaching out to us. I really appreciate your effort in explaining the problem description in so detail. 

    Looking at this below waveform, it seems when you are applying an input voltage very close to UVLO thresholds, the GATE pin is toggling. This is because the device enters into the UVLO hysteresis band. There are two ways to solve.

    1) Place a 100-nF ceramic capacitor across UVLO pin and GND. 

    2) Increase the hysteresis band by following the 9.2.1.2.6 Set Undervoltage and Overvoltage Threshold section in the datasheet. 

  • Hi Avishek,

    Thank you.

    I have added a 100nF capacitor across UVLO and GND and increased the hysteresis as shown below:

    Unfortunately, this has not resolved the issue. Although it did resolve the ringing phenomenon on the UVLO pin, now I observe other anomalous phenomena.

    Sometimes, the voltage across the UVLO pin reaches about 10V (which shouldn't happen due to the distribution resistors on the board). My suspicion is that the LM5069 is pushing current to R2 (?).

    In some cases, even the voltage distribution resistors have burned out. Based on my design, the maximum power dissipation on R1 and R2 shouldn't exceed 5mW (at VIN=20V), so I can't understand the reason for this phenomenon.

    Please find attached snapshot and a short video.

    The voltage across UVLO pin behaves chaotically.

    Video_2D00_1.mp4

      

      

  • Hi Yakavo,

    Are these two circuits (you mentioned to ignore those circuits) populated on your board? It's surprised to me if VIN is clean and stable how the voltage at the UVLO can have so much ripple. 

    Is the 100-nF ceramic capacitor is connected across R418? Still are these ripples there on the UVLO voltage?