TPS53688: Intel VRTT Transient_LL issue

Hello,

Please send config file & VRTT failing result waveform. We might be able to suggest suitable tuning parameters.

Thanks,

Travis

Hi Travis,

Here is the config file, VCCIN is the Rail#1 with 4phase design.

 TPS53688 4.0 Address 94 Project File_20230914.xml

We have complete DVID test cases, here we changed Dynamic ACLL to 0.625mohm to pass all the DVID cases.

When you tune parameters, please keep DVID test NOT impacted as we don't have resource to re-test DVID cases. :(

Here is the failing waveform. 3D worst case is 100Khz, 90%duty. 

Vdrop measured is 1.524V, and result is ~30mV over spec.

TPS53688 4.0 Modified Project File.xml

Hi Neo,

Looking at the config and waveform I would start by looking at reducing the DCLL, this will push the waveform up and help with the Vdroop. In terms of setting an accurate DCLL we can look at a few waveforms and compare to limits. The Vout waveform should be centered in the middle of the VMax and VMin.

In terms of ACLL and DCLL as a rule of thumb we recommend keeping them within 3-5x of each other so there is lots of room to lower ACLL to improve transient response in this system.

Static LL is largely effected by ramp, lower ramp => less ripple and at the cost of increased PWM jitter.

Separately, there is also undershoot reduction which can be enabled after loop compensation parameters have been tuned. These values should be progressively lowered, keeping USR2 higher than USR1, until the effect takes place.

Attached is an example config with some of these changes, but any changes would need to be tested on the board.

Let me know if further assistance is needed. 

Thanks,
Ryan

Hi Ryan,

As i mentioned, reducing ACLL does works. But TI has reported the DCLL and ACLL issue, that they should be kept same to make sure the load line is accurate at high current. So, AC loadline has to be kept same ad DCLL, which is 1.7mohm.

Will try with nonlinear parameter tunings and get back to you.

Thanks.

Verified that USR1/USR2 has no impact to Transient_LL Vdrop voltage.

Per datasheet, this is for phase shedding applications, but in my design, phase shedding is disabled.

Also tried RAMP, only 1-2mV impact.

Tuning AC load line to below 1.5mohm can pass Vdrop test, but Static LL case failed due to incorrect DCLL cased by mismatching between AC/DC loadlines.

How to proceed? Has TPS53688 been tested for VRTT?

Thanks.

Hi Neo, 

Still looking in to this, will reach out by end of week. Is the DCLL of 1.7mohm a platform specific requirement or can it be lowered, I am seeing a typical value for VCCIN DCLL much lower used for our testing.

Also to confirm, the static LL is failing because of a changed slope at large currents? Asking because this mismatch issue is typically seen when ACLL and DCLL are multiples apart from each other. 

Thanks,

Ryan

Hi Ryan,

DCLL 1.7mohm is hard requirement by Intel CPU.

Here is what we observed while keep DCLL=1.7mohm, while modify ACLL from 1.7mohm to 1.53mohm.

The slope got changed at high current. 

Thank you for providing this data, I'm going to see if it is reproducible on our EVM. We have testing with this part on a few platforms, which Intel platform specifically are you using? 

Thanks,

Ryan

Icelake-D LCC CPU from Intel.

Thank you, still looking into this, will reach out with more information next week. 

Hi Ryan,

Any further update on this?

Thanks

Neo

Still working on this, a quick solution would be to lower DCLL slightly to have the high current end still be in specification. I'm anticipating delays due to the holidays. 

Thanks, 

Ryan

Hi Neo,

I was able to reproduce these results on an EVM pulling 140A. For the ACLL DCLL mismatch I am seeing the Static LL issue from ACLL ~1.5mOhm  to ~1mOhm with fixed 1.7 DCLL, going below 1mOhm ACLL the static LL behavior goes away. Can you try running the test below 1mOhm ACLL and see if this fixes the static LL and is able to pass transient on your end? As a heads up, going from 1.5mOhm to 0.9mOhm ACLL may require slightly altered loop compensation parameters to pass.

Thanks,  

Ryan

Hi Ryan,

Changing ACLL to below 1mohm does not work for my case.

With 0.85-0.95mohm ACLL, i do see static LL passed, but transient LL Vdrop still failed with 15mV lower than spec.

However when reducing ACLL from 0.85mohm to lower value, we got Transient LL passed but Static LL failed again.

The window to pass both Static and Transient LL test is quite tight. I am not able to pass both tests with margins.

If you can share your email address i can send more data capture in our testing.

Thanks

Neo

Hi Neo, 

I will reach out in email as well, in terms of the tuning a few changes which may help, lowering TBLANK from 75 to 50, increasing integral time constant to 4us and changing AC Gain may help. 

Thanks,

Ryan