There have been multiple unresponsive issues during debugging 76952, and currently the problem cannot be found. Therefore, there are a few questions that need to be consulted:
Does 1 76952 require sequential startup or default startup when powered on, such as the need to pull down the wake signal
What is the state of REG1 before power on without configuration, whether it is suspended or has internal pull-down,
When the 76952 is not working, the clock signal of the ARM side SCL flips (position I2X1_SCL in the figure below), but the 76952 side SCL_ AFE is in a no signal situation, is there an internal pull-down on side 76952. What is the pull-down impedance?
When debugging BQ76952, we found that during high current (20A) charging, the voltage in the first section was about 200mV higher than the other sections, which has been verified as the cause of non battery imbalance.
We will use 76952 for 15 strings, with a short circuit in the next section. The balancing method is passive balancing of parity controlled by the host, with the cell being the real battery cell. The problem is when the cell_ When balancing is turned on at 15 (VC14-VC16), Cell_ The voltage of VC13-VC14 increases by about 20-40mV. 76952 Passive Equalization Timing Introduction: During voltage sampling, the equalization of active and adjacent nodes will be disabled. (VC14-VC16) and (VC13-VC14) are not adjacent nodes, so theoretically, VC13-VC14 can still be sampled normally when (VC14-VC16) is balanced. But in the scenario of 15 series usage, due to a short circuit in the secondary section, (VC14-VC16) and (VC13-VC14) became adjacent sections. At this time, normal sampling during equalization will lead to low section voltage and high section voltage. How to handle this situation?
1. As shown in the figure below, we will use 76952 as a 15 string, with a short circuit in the secondary section. The balancing method is passive balancing of parity controlled by the host, with the cell being the real battery cell. The problem is when the cell_ When balancing is turned on at 15 (VC14-VC16), Cell_ The voltage of VC13-VC14 increases by about 20-40mV. 76952 Passive Equalization Timing Introduction: During voltage sampling, the equalization of active and adjacent nodes will be disabled. (VC14-VC16) and (VC13-VC14) are not adjacent nodes, so theoretically, VC13-VC14 can still be sampled normally when (VC14-VC16) is balanced. But in the scenario of 15 series usage, due to a short circuit in the secondary section, (VC14-VC16) and (VC13-VC14) became adjacent sections. At this time, normal sampling during equalization will lead to low section voltage and high section voltage. How to handle this situation?
We found that 76952 exhibited intermittent IIC communication when tested for high temperatures in a constant temperature box at around 80 ° C. This phenomenon can also be replicated by blowing 76952 alone with a hot air gun at room temperature,
Preliminary software investigation revealed a communication fault while reading voltage. During the IIC read operation, the host timed out waiting for ACK after sending the slave address, reporting a communication failure. After detecting IIC communication failure