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LM5158: Layout QFN Pad-to-Pad isolation

Sebastien Gravel
Prodigy 20 points
Part Number: LM5158
Other Parts Discussed in Thread: LM5155

Hi, 

We are using this chip to do 12V -  54V and when entering our layout rules for clearance (IPC2221A for 54V). We noticed that the pad-to-pad clearance for the pin 13-14 versus the thermal pad aren't within the IPC2221A specification. Is there any layout consideration that should be taken to maintain proper isolation for this QFN ? Any conformal coating is needed to help with this ?

Best Regards,
Sebastien

  • 0
    TI__Mastermind 31910 points

    Hi Sebastien,

    Thanks for using the e2e forum.

    I am not familiar with the IPC2221A limitation, so I do not know if the LM5158 package fits these requirements.
    Pin 13 and 14 are the SW pin.
    Can you give more details on the application background to better understand the isolation requirements?
    It would be helpful to know:
    - topology of the design?
    - 12V-54V, is this the input voltage range, or is it a boost design that boosts from 12V to 54V?
    - max load requirements

    With this data, I can also look for LM5158 designs that already have a finished layout, so you can take this for reference.

    Thanks and best regards,
    Niklas

  • 0 in reply to Niklas Schwarz
    Prodigy 20 points

    Hi Niklas,

    It is a boost design that takes 12V +/-5% and boost it to 54V.
    The max load will be 200mA.

    Pin13 and Pin14 are SW and from my understanding, these pins should reach the maximum voltage of 54V.
    The IPC2221A specified that the clearance for isolation between two conductors at 54V peak would be 24mils (0.6mm) without any coating on external layer so I'm wondering if there is anything that needs to be done on the layout to make sure we have proper isolation. 
     
    I have looked at the evaluation board file but couldn't find if anything special was done to the layout to have isolation or if it is even actually needed. 

    Best Regards,

    Sebastien

  • 0 in reply to Sebastien Gravel
    TI__Mastermind 31910 points

    Hi Sebastien,

    Thanks for the update.
    The best reference board for LM5158 is indeed the EVM, which is only set for a Vout of 12V, but I did not find other resources that address any specific precautions for IPC2221A conform implementations.

    The pin layout of LM5158 shows that the directly adjacent pins are NC, so the only clearance constrain is the bottom pad.

    However, the bottom bad is for heat dissipation only, so it is not essential for the Boost application.
    Common designs connect the ground pad to the board ground to allow better heat dissipation, but if the clearance cannot be provided, the EP pad could be left floating or connected to an isolated GND on the cost of worse thermal performance.

    Another alternative would be to switch to a controller with external switch (e.g. LM5155). This will increase BOM cost, but it would be easier to guarantee enough clearances for all 54V lines.

    I am very sorry for our lack of data for this topic.
    Please let me know if you have additional open questions on any of the mentioned devices.

    Best regards,
    Niklas

  • +1
    Prodigy 20 points

    After some research, I found out for IC that it is a different specification. 

    Pin to pin issue is functional issue and not a safety issue. Safety is ensured by dielectric strength tested by hipot test.

    UL62368-1. The spacing in this standard depends on the Pollution degree and material group. According to UL standard (table 2N) up to 80V minimum creepage for pollution degree 1 is 0.22mm and for 63V – 0.2mm. For IC with 0.5mm pitch, distance between pin is 0.2-0.25mm and therefore it meets UL safety requirements.

    Thanks,

    Sebastien