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UCC28061: MOSFET Failure

Part Number: UCC28061


Hi,

We are using UCC28061 as a controller in our interleaved PFC design. We are dealing with the MOSFET failure after turning off/on the board. After turning off, we detected that the MOSFET in PFC circuit goes to short circuit in the case of cut-off. As can be seen in the scope view, at the turn off condition, the transient drain current is10A and after the gate voltage turns to cut-off situation, ringing occurs at the MOSFET gate terminal. As recommended in the datasheet, to eliminate damp ringing, we also put a small series resistance (10R) to gate drive, but the ringing continues to show up which causes short circuit of MOSFET as can be seen in below.

We detected that gate is drived involuntarily that forces to turned on the MOSFET (Not in linear region)

What could be the cause of this behavior?

Do you have any solution for this unexpected behavior?

Yellow: Drain Voltage (100V/div)

Blue: Drain current (5V/div)

Green: MOSFET Gate voltage (20V/div)

Time div:40ns

 

 

 

 

 

  • Hello,

    I am reviewing your inquiry and will get back to you shortly.

    Regards,

  • Hello,

    Looking forward to hearing from you.

    Best Regards

  • Hello,

    Did you see the response below?

    Regards,

  • Hi,

    Layout update is not in the schedule right now. So, we will increase the gate resistor to 20ohm accepting the probable high loss on the MOSFET. Is there any constraint for the value of gate resistor?

    Regards

  • Hello,

    Your inquiry is under review and I will get back to you shortly.

    Regards,

  • Hello,

    You are correct that adding a gate drive resistor will increase the losses of the FET.  This will be due to having less current to charge and discharge the gate capacitance of the FET.  This will result in increased switching losses.  However, the conduction losses should relatively remain the same.  This is because the gate voltage will be driven to the same level.  

    The following equations can be used to estimate FET turn-on and turn-off times.  Where Radded is the gate drive resistance you add from GDA_B to the FET's gate.

    FET turn on drive current (Idrive1).

    Idrive1 = VDGA_B(Radded + (GDA_B on-resistance_high))

    FET turn off sink current (Idrive2).

    Idrive2 = VDGA_B(Radded + (GDA_B on-resistance_low))

    dQ is difference between the gate charge at the end of the miller plateau and the gate charge at Vgs(th) of the FET.

    This information can be found in the FET data sheet. 

    FET turn-on time (dton):

    dton = dQ/Idrive1

    FET turn-off (dton):

    dton = dQ/Idrive2

    The increased switching losses could result in require additional FET cooling and heat sinking.

     

    Regards,