We are entrusting USB authentication, TEST_ Attempting to change the relevant configuration of the chip in J mode, the experiment found that CTL1 and 2 were set to SDP mode, and the DM voltage was measured to be 4.7mV in J mode; Set CTL1 and 2 to CDP mode, and measure the voltage in J mode as DM22.5mV;
In SDP mode, although test_ The voltage of J is low, but there are several U-disks that cannot be recognized;
Certification determination requirement TEST_ In J mode, the DM is lower than 20mV, so please help to check our schematic where there is an issue with the hardware configuration (such as current limiting resistors, etc.). Please analyze and provide support. Thank you. Attached is a schematic diagram of the design.
We tend to use SDP mode for testing_ In TEST_J mode, the voltage may be too low and pass the certification test, but we are not sure if there are any side effects, such as a decrease in USB recognition ability. We can still mount HUB outside our host, so the host does not provide fast charging to customers, and the hub provides charging function.