TPSM846C23: TPSM846C23-Schematics Review (5V to 0.65V&0.75V)

Sujith Mohandas

Part Number: TPSM846C23

Hi Team,

I have done a high current step down converter design using TPSM846C23 power modules.Please see my below requirement and schematics capture for design 1.

Design -1

VIN=5V
VOUT=0.65V
IOUT=70A
FSW=500KHz
Vout allowable Transient should be less than 2% of VOUT(0.65V)

Schematics capture 5V to 0.65V @70A

/cfs-file/__key/communityserver-discussions-components-files/196/TPSM846c23_5F00_Schematics.pdf

Kindly check the above schematics and let me know your review feedback, can we achieve the transient response using above design compensation values?

Design -2

VIN=5V
VOUT=0.75V
IOUT=70A
FSW=500KHz
Vout Allowable Transient should be less than 2% of VOUT( 0.75V)

Can i use schematics 1 design for Design 2 requirement? Please let me know if there any modification has to done to meet the transient response?

Regard,
Sujith M

over 1 year ago

+1 Athos Zhao over 1 year ago

TI__Expert 7320 points

Hi Suijith,

Our US team will reply you after the holiday.

+1 Sujith Mohandas over 1 year ago in reply to Athos Zhao

Prodigy 190 points

Hi Athos,

is there any updateS on my request ?

Thanks,
Sujith

+1 Caleb Perez over 1 year ago in reply to Sujith Mohandas

TI__Genius 11315 points

Hey Sujith,

Taking a look at this now. I'll have an answer soon.

Thanks,
Caleb

+1 Caleb Perez over 1 year ago

TI__Genius 11315 points

Hey Sujith,

I believe this setup may work. Your ripple requirement of 2% most definitely will be met, but any actual transient estimation would require a load step and a slew rate. I recommend you build a board to validate performance. I used the PSPICE model available on TI.com to verify the 2% ripple. You should be able to access it too.

This setup should also work for 0.75Vout.

Thanks,
Caleb

+1 Sujith Mohandas over 1 year ago in reply to Caleb Perez

Prodigy 190 points

Hi Caleb,

Thanks for your review.

Still,i would like to know the best suitable compensation network for 5V to 0. 75V.In Below table i couldn't find any stright comp network.
Could you please confirm same?

/cfs-file/__key/communityserver-discussions-components-files/196/pastedimage1704813752418v1.png

Regards,
Sujith M

+1 Caleb Perez over 1 year ago in reply to Sujith Mohandas

TI__Genius 11315 points

Hey Sujith,

You should use the compensation network that aligns closest to your vout. You could try to see how the device performs with the compensation used at 0.65V, and compare it to the compensation suggested for 0.8Vout.

Thanks,
Caleb

+1 Sujith Mohandas over 1 year ago in reply to Caleb Perez

Prodigy 190 points

Hi Caleb,

Thanks for your feedback.
May i know,in this stacked mode if i want to change the Switching frequency can i change the clock source part with some other part ?currently i have referred Evaluation board clock source part in my design. is there any special recommendation for clock source?

Is there any other feedback on my schematics ? Output and input capacitor filter section ?

Regards,
Sujith M

+1 Caleb Perez over 1 year ago in reply to Sujith Mohandas

TI__Genius 11315 points

Hey Sijuth,

You can used any clock source provided it meets the requirements outlined in table 6.6 of the datasheet. See "SYNCHRONIZATION" parameters.

I think your input and output capacitor is okay since you have followed the recommendations of the datasheet. It may need change depending on your transient requirements, but you won't know until you test the design on a bench.

Thanks,
Caleb

+1 Sujith Mohandas over 1 year ago in reply to Caleb Perez

Prodigy 190 points

Hey Caleb,

Thanks for your review and supports.

Do you have any schematics and layout checklist for this power modules?

Thanks,
Sujith M

+1 Caleb Perez over 1 year ago in reply to Sujith Mohandas

TI__Genius 11315 points

Hey Sujith,

Schematic and Layout checklist is attached below.

Thanks,
Caleb

TPSM846C23_Schematic_Layout_Checklist.xlsx

+1 Sujith Mohandas over 1 year ago in reply to Caleb Perez

Prodigy 190 points

Hi Caleb,

Does this stacked TPSM846C23 device supports Vout setting using hardware strap resistor?

Regards,
Sujith M

+1 Caleb Perez over 1 year ago in reply to Sujith Mohandas

TI__Genius 11315 points

Yes. You can use Rset to set the output voltage.

If you think this solved your question, can you please click " This resolved my issue."

Thanks,
Caleb

+1 Sujith Mohandas over 1 year ago in reply to Caleb Perez

Prodigy 190 points

OK Thanks for confirm

+1 Sujith Mohandas over 1 year ago in reply to Sujith Mohandas

Prodigy 190 points

Hi Caleb,

I have doubt on output Decoupling capacitors selection, for stacked configuration how many non-Ceramic capacitor to be added in the design ?

For each module how many should be populated?

Could you please confirm below table Cout capacitor count recommendation is for standalone or parallel configuration ?

/resized-image/__size/734x699/__key/communityserver-discussions-components-files/196/pastedimage1709035364695v1.png

Regards,
Sujith M

+1 Tahar Allag over 1 year ago in reply to Sujith Mohandas

TI__Mastermind 32350 points

Hello,

Caleb is OoO, i am jumping into this. use 2x47uF for each device (total 4), the closest possible to the IC, then use the none ceramic for the rail as in the EVM below.

https://www.ti.com/lit/ug/slvub26d/slvub26d.pdf?ts=1709073768187&ref_url=https%253A%252F%252Fwww.google.com%252F

Thanks!

Tahar

+1 Sujith Mohandas over 1 year ago in reply to Tahar Allag

Prodigy 190 points

Hi Tahar,

Thanks for the input, i have updated the schematics according to your feedback.

I have a doubt regarding the PMBus Pull up voltage of TPSM846C23MOLR.I could not figure out the exact pull up voltage of PMBus DATA,CLOCK and ALERT signal.?
As of now in my design all PMBus control signals are pulled up with VCC_3V3 ? is it proper connection ?
Could you please check and let me now the pull up Voltage of this device ?

Schematics design pdf:
/cfs-file/__key/communityserver-discussions-components-files/196/TPSM846c23_5F00_Schematics.pdf

Regards,
Sujith M

+1 Calan Elaya over 1 year ago in reply to Sujith Mohandas

TI__Genius 11125 points

Hi Sujith,

A response will be posted in the next couple of days.

Thank you,

Calan

+1 Caleb Perez over 1 year ago in reply to Sujith Mohandas

TI__Genius 11315 points

Sujith,

The CLK, DATA, and ALERT lines can handle an absolute maximum voltage of 5.5V. Your pullup of 3.3V will be fine.

Thanks,
Caleb

+1 Caleb Perez over 1 year ago in reply to Caleb Perez

TI__Genius 11315 points

Furthermore, the requirements for the PMBus interface can be found here.

+1 Sujith Mohandas over 1 year ago in reply to Caleb Perez

Prodigy 190 points

Hi Caleb,

Thanks for confirm

Regards,
Sujith M

0 Sujith Mohandas over 1 year ago in reply to Sujith Mohandas

Prodigy 190 points

Hi Caleb,

I have a question about external synchronous clock sourcing for TPSM846C23 stacked power module. Is there any timing between the module input voltage and the external sync clock input.

which one should be enabled first? Will it work if we provide external sync clock input before sourcing VIN?

As of now in my design VCC_3V3 power up first and it will enable sync clock source ,after 5ms VIN 5V is powered up the stacked Module.

Regards,
Sujith M

0 Calan Elaya over 1 year ago in reply to Sujith Mohandas

TI__Genius 11125 points

Hi Sujith,

A response will be posted in the next couple of days.

Thank you,

Calan

0 Sujith Mohandas over 1 year ago in reply to Calan Elaya

Prodigy 190 points

Hi calan,

Any updates?

Regards

Sujith

0 Tahar Allag over 1 year ago in reply to Sujith Mohandas

TI__Mastermind 32350 points

Hello Sujith,

Yes, it will. There must be an external sync clock presented to the master at the SYNC pin for parallel operation. Section 7.3.20 Parallel Operation details this. "The SYNC pins of the master and the slave must be supplied with a 50% duty cycle clock signal at the desired switching frequency". This ensures that they are running at the same frequency with minimal delays.

Both the master and slave module must have an RRT resistor present whose value sets a switching frequency within ±20% of the SYNC clock frequency. When power is applied, if no external clocking signal is present on the SYNC pin, the device operates at the switching frequency set by the internal or an external timing resistor. It is permissible for the SYNC signal to become active after the module has powered up.

Thanks

Tahar

0 Sujith Mohandas over 1 year ago in reply to Tahar Allag

Prodigy 190 points

Hi Tahar,

Tahar Allag said:
When power is applied, if no external clocking signal is present on the SYNC pin, the device operates at the switching frequency set by the internal or an external timing resistor. It is permissible for the SYNC signal to become active after the module has powered up.

So basically, there won't be any issue if we supply SYNC clock before power on the module?

One more question is,Does stacked TPSM846C23MOLR module will work without external sync clock. Can we utilize internal clock?

Regards,
Sujith M

0 Tahar Allag over 1 year ago in reply to Sujith Mohandas

TI__Mastermind 32350 points

Hello Sujith,

Yes, it is correct. no need for external clock. However, both the master and slave module must have an RRT resistor present whose value sets a switching frequency within ±20% of the SYNC clock frequency.

Thanks!

Tahar

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TPSM846C23: TPSM846C23-Schematics Review (5V to 0.65V&0.75V)