TPS61220: TPS61220DCKR

Hi 
It’s normal ripple larger for light load condition. But it won’t  be as large as 50mV. Please use smallest circle to test the output ripple where it’s as close as possible to the Vout pin. Otherwise could you try TPS61299 the ripple is smaller.

Thank you for your answer. But I am not sure that I understand you.

1. TPS61299 cannot be used in my design because it is too expensive. This is disposable device.

2. As I understand, you say that ripples shall not be 50 mV even with light load. But see photo from oscilloscope. Ripples even exceed 50 mV. What may be wrong? What do you mean smallest circle to test the output ripple?

Thank you

Hi Michael, 

As you can see in below figure the output ripple is typically 20mV. Please use smallest circle to test the output ripple.

Also could you use the offset and zoom in the ripple waveform?

Hi!

Attached zoom of ripples. DC level 3.3V. Pictures from datasheet that you have sent looks not relevant, because load current in one picture is 10 mA and in another 50 mA.

As I wrote in my design load about 2 mA

Is anyway to reduce ripples on such load without increasing capacitor.

Best regards

Michael

Hi

I mean although the datasheet shows 10mA load, the typical theory is the same with 2mA load, because it's also working under PFM mode.

Adding to capacitance is of some help to reducing the output ripple. What is the requirement about Vout ripple. Also is Vin 1.5V? Could you also test the SW waveform?

Input is 1.1V -1.5V. It is a battery AAA or Coin.. Because coin battery I cannot increase load capacitor because inrush. Ripples shall be about 10-15 mV maximum. But not 60-70 mV as here. I am not sure what is SW. Do you mean L pin 5. If yes, attached

There are 2 ceramic capacitors 10uF and 100 nF on the output of DC-DC converter as recommended in datasheet. I cannot increase capacitor because higher inrush current during switching device on. any idea?. 

I mean is there any effective capacitance descending due to DC bias.  Please check the effective value .

By the way you can send me e-mails for detailed discussion and the customer's application.

My e-mail is nini-zhong@ti.com

Thank you. I see that capacitor in my design is 10 µF ±20% 6.3V case 0402.ceramic Capacitor X6S 0402 (1005 Metric). But in TI reference design it is X5R . But in TI EVB capacitor is 10 µF ±20% 6.3V Ceramic Capacitor X5R 0603 (1608 Metric). Can this cause problem that you mentioned?

Firstly you should check the effective capacitance according to the datasheet of 0402 ceramic capacitor.

Could you try to double the capacitor , that may be fo help to cut down the ripple in your application.

I checked and it looks really bad.  0n +3,3V bias it is -62% regarding to nominal 10 uF capacitance that means about 3.8 uF really. I will add additional same capacitor   in parallel to existing and test. 

Okay~ Close this thread and if you still have any questions then you can send me e-mail :nini-zhong@ti.com