LM5171-Q1: LM5171-Q1 EVM _I2C communication .

Hi,

Please find below sequence we are following in software, while communicating with the EVM using I2C,

1. Start Condition
2. Master sends Slave address - 0x00 with R/W bit as 0 : Slave is responding with ACK
3. Master sends Register address - 0x78 (0x78): Slave is responding with ACK
4. MSSL + Repeat Start Condition
5. Master sends Slave address - 0x00 with R/W bit as 1: Slave is responding with ACK
6. Getting response as 0x30 consistently ( not changing this response if we create any new fault )
7. Stop condition.

Also, instead of 78 if we try to send out register address D0/ D1 its still sending 0x30 as read data .

 Above commands are implemented as per the format specified in the datasheet https://www.ti.com/lit/pdf/SNVSC75 , page 41

Can you able to share sequence/flow diagram, standard document are following while communicating with slave, also at what clock frequency.