How to test the jitter on switch node in D-CAP POL?

Kevin,

Depending on the capabilities of your oscilloscope, you could probe the switch node, trigger first on the rising edge and then on the falling edge, increase the persistence and then maximize the time base (or zoom) to most effectively display all the edge data. Once captured, you can then measure the Δt jitter and do this for the rising edge and then the falling edge. You can express Δt jitter as a percent of the nominal switch node pulse width or if your oscilloscope allows, display a histogram to provide a visual representation of the statistical distribution of the measured Δt jitter.

If you have additional questions specific about D-CAP, please submit a new E2E thread with the TI part number in the title so the appropriate product expert can be assigned to help. 

Regards,

Steve

Kevin,

when you say "the chip", what chip? For some controllers you should expect zero jitter and the observance of jitter would only be a result of the presence of noise seen by the PWM. For other controllers, TI might use frequency dithering as a technique to help mitigate EMI and for these controllers, the dithering depth determines the expected amount of jitter. Some digital control algorithms use dithering techniques to help locate an optimal operating point such as reducing body-diode conduction by minimizing dead time. So I guess the answer to your question is, "it depends." If you have question related to a specific TI device, I would suggest to submit a new E2E with the device part number in the title, then you should expect an exact answer about dither related to that device.

Regards,

Steve