LM5176-Q1: LM5716 power on delay time

Hi Michael,

thank you for supporting the LM5176.

After EN high the Vcc LDO will be enabled and once this LDO has settled the controller starts to charge SS cap and start operation.

As this EN high to start switching depends on external components this can not be specified in the datasheet.

May you can explain the issue you see, so that we can help solving the issue.

Best regards,

 Stefan

Hi Stefan,

Normally, the time for EN high to starting switching shall be decided by chip internally, soft start timed is decided by external capacitor.

As picture below shown, power on delay time is defined in TI TPS6281x datasheet as an example.

So please provide this parameter.

Thanks!

Michael

Hi Stefan,

     Thanks for reply. This parameter maybe already available, right? If is, could you kindly please get it from other person or someway else? As we need it to deal with a urgent problem, thanks for understanding!

Michael.

Hi Michael,

I already check the char data and other sources but it was not listed there. So the last source I see is simulation or design data analysis.
Will track and give feedback as soon as possible.

Best regards,

 Stefan

Hi Stefan,

Thanks for reply.

For EN pin, is it edge trigger or voltage level trigger？ If EN falls below EN UVLO，how long shall this status keep, then LM5176 can recognize EN OFF?

Thanks!

Michael.

HI Michael,

this delay depends on VIN rise time and the connection between VIN and enable.

Can we assume the condition you showed above: Vin already ramped and EN level change in a few ns?

Best regards,

 Stefan

Hi Stefan,

Thanks for reply!

Yes, you are right. Vin already ramped, and EN level changes in a few us.

If EN falls below EN UVLO，how long shall this status keep, then LM5176 can recognize EN OFF?

Thanks!

Michael.

Hi Michael,

thanks for confirming, will check with design with that parameters.

Best regards,

 Stefan

Hi Stefan,

Please provide these two parameters:

1. power on delay time, min/typ/max value;

2. If EN falls below EN UVLO，how long shall this status keep, then LM5176 can recognize EN OFF.

We need it a little urgently, a few days passed, please provide!

Thanks!

Michael.

Hi Michael,

design is working on this but Spice simulation takes some time.

Note: As this data is only available from design simulation, I only can provide typical numbers. For min/max a characterization data would be required but this is not available for that.

Best regards,

 Stefan

HI Michael,

we could get the results now out of simulation.
Note: this is simulation data only - not measured on real silicon.

The delay between EN going high and start of operation (with VIN already ramped up before) can be up to 500us.

The delay for EN low to switch off will be lower then 5us.

Best regards,

 Stefan

Hi Stefan,

Thanks for reply!

What's min value of "The delay between EN going high and start of operation (with VIN already ramped up before)"?

Thanks!

Michael.

Hi Michael,

the min time for EN high to start operation can go down to below 100ns.
This and also the above mentioned parameters highly depends on the used external components.
For this simulation following config was used:

VIN=12V and C_VCC=1uF and C_boot1=C_boot2=100nF
Esp. for the min time the charge time of the caps will have a big impact.

Best regards,

 Stefan

Hi Stefan,

     Thanks for reply!

     This means that min value is 100ns, max value is 500us. If "VIN=12V and C_VCC=1uF and C_boot1=C_boot2=100nF", considering tolerance of capacitors, could you explain why the gap between min and max is so huge?

     As we mentioned above for TI TPS6281x, this parameter is from 135us to 470us.

Thanks!

Michael

Hi Michael,

this time highly depends on external components.

E.g. Charging of the caps and the internal logic will detect and enable functions when OK signals ensure the voltages have settled.

I do not know how this is implemented in the TPS6281x as this belongs to a different team.

Once again also the parameter above are just indications as this are based on simulations. 

Best regards,

 Stefan

Hi Stefan,

Yes, understand.

Based on "VIN=12V and C_VCC=1uF and C_boot1=C_boot2=100nF", then external components are fixed, generally, we would still think that gap between min and max is so huge. 

Could please kindly help confirm for min value? As we really need this parameter to implement power on strategy.

Thanks so much!

Michael.

Hi Michael,

sorry, I can not provide more info/details as additional data is not available.

Best regards,

 Stefan

Hi Stefan，

As we mentioned above, power on delay is from EN high to starting operation(switching), that is t3 in tested wave below of LM5176.  It includes two phases: EN high to soft start beginning(t1 in wave below), soft start beginning to starting operation(t2 in wave below).

For t2, it's also from soft start beginning to SS capacitor voltage reaching Vx(70 mV in wave below), and this time is about Vx/Vref(0.8V) of whole soft start duration, t2=Vx/Vref*(Css*Vref/Iss)=Vx*Css/Iss, which depends on external soft start capacitor.

So t3=t1+t2, if external soft start capacitor is not pF, power on delay can't not be ns level.

Stefan, could you please share us the parameter Vx (soft start capacitor voltage when starting operation) ?

And please double confirm simulation process, for example ,the external soft start capacitor value in simulation?

Many thanks!

Michael.

HI Michael,

i will check with design again.

Best regards,

 Stefan

Hi Stefan,

So time for for EN high to start operation, min value is 97us, and max value is 560us，right?
Thanks!

Michael