Hello,
The waveform in Fig1 can be seen every few times during burst mode under light load.
What is this happening?
I usually use Fig2 most of the time.
Is this normal? Are there any countermeasures?
I'm working on increasing the efficiency of light loads.
I think it would be even better if this was removed.
regards
Wave form_Light Load.pdf
Hello,
Please note both of your waveforms have excessive ringing on the transformer that should not be present. You may want to figure out what is causing this ringing and remove from your design. This could be caused by layout/schematic errors.
In Figure 1 you are correct that the polarity across the transformer should change every other cycle including burst mode. So you should not see that behavior.
There is a 600 W reference design using the UCC28950, UCC28950EVM-442 that you may want to order and evaluate. The following link will bring you to the user's guide for this evaluation module. There is a schematic, layout and test data in this User's Guide that you may want to evaluate. https://www.ti.com/lit/ug/sluu421a/sluu421a.pdf
The waveform below was taken from the 600 W UCC28950 evaluation module. CH1 is the voltage across the transformer and shim inductor. CH4 is the CS signal and CH2 and CH3 are the low side FET gates. From these waveforms you can see there is not excessive ringing that is present in your waveforms.
The User's guide has what the behavior should look like in burst mode. Below in figure 23 is the behavior that you should observe in burst mode. The voltage across the transformer should change polarities every other cycle.
When looking at your waveforms in light load burst it looks like you minimum duty cycle is set for 40%. This is kind of high and may be causing some of your issues. Pin Tmin of the UCC28950 sets the minimum duty cycle before bursting. You might want to set RTmin to 10 k ohm to see if the issue goes away. This will give a minimum duty cycle of 50ns*(switching frequency) before bursting.
The following link will bring you to an application note that goes through the step by step design process of phase shifted full bridge using the UCC28950 PSFB controller. There is even a link inside the application note to an excel design tool that uses the same equations as what is presented in the application note. You can use both the application note and excel design tool to design to check your design.
https://www.ti.com/lit/pdf/slua560
Regards,
Hello,
You could be right about the inductor resonating because the inductor is gong DCM. You can verify this by studying the inductor current versus the waveform that you have taken to verify this.
The shim inductor will form a voltage divider with transformer primary magnetizing inductor. As long as the value is not too large it should not cause an issue. I would think if it was 10% or less compared to Lm it would not cause an issue.
If your RTmin is set for 15 k ohms your minimum voltage applied the transformer should be 75 ns. Even though the controller is bursting it may not be due to light load bursts controlled by tmin pin .
You might want to study COMP, CS, SS and the voltage across the Transformer and Shim inductor. This may give you a clue to why the design is bursting.
I reviewed the schematic that you had attached and see that is of the power stage, H Bridge Driver and the current sense transformer; as well as, the output rectifiers. The controller section and output filter was not present. I see that you have snubbers across the output rectifiers that could be used to dampen the DC ringing that you observe across the primary of the transformer. This may help with EMI as well.
I also noticed that you used clamp diodes between the shim inductor and the primary of the transformer. A log of engineers miss this and they are required to protect the secondary rectifiers from over voltage.
Regards,
Hello,
If both phases are not free wheeling the voltage across the transformer will be the on time. If you wanted to determine the exact on time based on the UCC28950 controllers, you would have to look at Out A .. Out D. When Out A and Out D on at the same time this will be the on time from the UCC28950. When Out B and Out C on at the same time this will be the on time from the UCC28950.
1. In regards to setting the minimum TMIN I would recommend only using resistors between 10k and 135k ohm. This is where TMIN was characterized.
2. There is a DCM pin that can be used to turn off the FETs before the current goes discontinues. This is set with a resistor divider from Vref to the DCM pin. If the peak current on the CS pin does not go above the DCM threshold the SR FETs will be disabled. Setting up this DCM comparator is covered in section 7.3.12 in the data sheet.
Regards,
