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UCC5350: Drive four SIC MOSFETs in parallel with a single gate drive for Miler clamp connection

Part Number: UCC5350

Dear TI Expert,

Good Day!

I'm using UCC5350MC to drive four SIC Mosfets(C3M0040120K) in parallel, and i would like to know Miler Clamp connection for all SIC Mosfets.

I refer to another miler clamp application discussion article, the circuit need to add PNP transistors to buffer the CLAMP signal and isolate the gates from each other.

Below are two topology of miler clamp application for SIC mosfets in parallel, could you help me to know which one is better and any parameters need to modify?

Note:

1. DRH_1~4 connect to SIC gate pin

2. G_DRH connect to SIC driver source pin

Figure1: 

Figure2: 

Thanks & Best Regards

  • Hi Chiayuan,

    Our expert is currently Out of Office in observance of an US holiday. We'll get back to you before end of this week. Apologies for the inconvenience.

    Best,

    Pratik

  • Hi Chiayuan,

    The Miller clamp for the UCC5350M was designed for easy use with one gate. It is more complicated to use with multiple gates.

    If you tie all of the gates to CLAMP with 0 ohms, then all the gates will be at the same voltage. If there was a small Vth difference between the 4 parallel gates, then there would be temporary unequal current sharing between the devices during turn-on and turn-off. This is the only non-ideal result if you do not buffer the CLAMP with parallel switches. It is not a huge problem, but it can be avoided if desired.

    I like the first image's idea of not using the CLAMP pin for conduction at all, and instead using a local PNP turn-off. Miller current injection is high frequency, and the length inductance (gate->driver-> back to fet source) is what limits the pull-down impedance. For parallel switches, a local PNP can minimize this loop much better than a long trace back to the gate driver. 

    To make this circuit work, you need to use the OUT pin, not the CLAMP pin, to drive the local PNP. It will stay on regardless of the voltage, whereas the CLAMP is only active below 2V. I can verify that this is an effective design that maximizes turn off current, eliminates Miller issues, and also isolates the gate voltages.

    Best regards,

    Sean