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UCC21750: VSI Upper switch pulse off time is not equal to lower switch pulse off time.

SOURABH JAIN
Prodigy 40 points
Part Number: UCC21750

Dear Sir,

We are test DSAT function on 3 phase VSI using UCC21750. 

Condition#1:

When upper switch pulse and lower switch short circuited.

Pulse off time for upper switch is around 1.338us and DSAT FLT report time around 300ns.

Upper switch VCE (C4 Green Color) [Inverter G3 PWM return tied with output V terminal]

DSAT FLT (Yellow Color)

Condition#2:

While lower switch pulse and upper short circuited. Pulse off time 2.184us and DSAT FLT report time again 300ns.

For Lower switch

Lower switch VCE (C4 Green Color) [Inverter G4 PWM return tied with output DC bus -ve]

DSAT FLT (Yellow Color)

I used 100pf as CBLK . and calculated tBLK time is around 1.8us. if we add “leading edge blank time” tDESATLEB around 200ns and tDESATOFF  (“DESAT propagation delay to OUT(L) 90% time”) ~300ns. then total time required around 2.3us.

But my upper switch low pulse within 1.338us.

Please guide us why we get two different times.

  • 0
    TI__Genius 13760 points

    Hi,

    Thank you for posting to E2E.

    It is normal for the DESAT timing to be different between high side and low side drivers due to DESAT protection being affected by the power stage transients(dV/dts and dI/dts coupling between nets due to system parasistics). The exact short circuit transient will have some differences between high side and low side drivers.

    In order to dig into this deeper it would be good to collect more information. I would recommend probing the following signal for the high side and low side driver for each experiment.

    • Signals to measure during high side short circuit test:
      • High side MOSFET GATE to SOURCE (Use differential or isolated probe)
      • High side MOSFET VDS (Use high voltage differential probe or measure switch node to power ground using single ended high voltage probe)
      • High side MOSFET drain current (Use rogowski coil)
      • High side MOSFET DESAT to COM voltage (Use differential or isolated probe)
      • If more than 4 channel scope also include high side MOSFET FLT pin (Use single ended probe)
    • Signals to measure during low side short circuit test:
      • Low side MOSFET GATE to SOURCE (Use use single ended probe)
      • Low side MOSFET VDS (Use high voltage single ended probe or high voltage differential probe)
      • High side MOSFET drain current (Use rogowski coil)
      • High side MOSFET DESAT to COM voltage (Use use single ended probe)
      • High side MOSFET FLT pin (Use use single ended probe)

    Best regards,

    Andy Robles

  • 0 in reply to Andy Robles
    Prodigy 40 points

    Hello Andy,

    We have only two isolated probes and do not have a Rogowski coil for the current measurement.

    We probe DESAT to COM (Red Color)

    Switch VCE (Green Color)

    DESAT FLT PIN (Yellow Color)

    High Side switch results 

    Low Side Switch results

  • 0 in reply to SOURABH JAIN
    TI__Genius 13760 points

    Hi,

    In the waveform for the high side switch it seems the DESAT pin signal doesn't reach the UCC21750 9V DESAT threshold, but the FLT pin is still going LOW.

    • Could you confirm this is the DESAT pin signal?
    • What type of probe are you using?

    On the high side driver waveform I can see the DESAT signal is going negative. This is due to the negative dV/dt on VCE during the switching transient. This negative dV/dt along with the DESAT circuit HIGH voltage blocking diode parasitic junction capacitance draw current from the DESAT node causing it to go negative. To reduce the effect of the dV/dt you have to choose a high voltage blocking diode with minimal junction capacitance.

    • Could you share the part number of the diode used in your design?

    Best regards,

    Andy Robles

  • 0 in reply to Andy Robles
    Prodigy 40 points

    Hi,

    Thanks for reply.

    Yes, red color signal is for DSAT, and it is probe across capacitor C73 using 10x probe.

    The diode part no. is S1MFP from onsemi.

  • 0 in reply to SOURABH JAIN
    TI__Genius 13760 points

    Hi,

    The diode seem to have a fairly low junction capacitance meaning it should be an issue, but it will still draw some current from the DESAT as mentioned below due to the junction capacitance and dV/dt.

    I would still like to take a close look at the DESAT pin signal. The signal is not going over the DESAT detection threshold (9V), but DESAT is still trigerring. Could you share a picture of how this is being probed? (For the most accurate representation of the signal being feed to the gate driver you would need to probe as close as possible to the gate driver pins).

    Another thing we can take a look at is the layout. Layout can add additional parasitics to the circuit that can effect the timing. Could you share screenshots of your layout showing the HIGH side and LOW side DESAT circuit design?

    Best regards,

    Andy Robles

  • 0 in reply to Andy Robles
    Prodigy 40 points

    Dear,

    Please find placement layout for U9


    and Placement for U8

  • 0 in reply to SOURABH JAIN
    TI__Genius 13760 points

    Hi,

    Thank you for the details. I will need a couple days to be able to take a thorough look at the layout. I will provide an update early next week. In the meantime please share any additional testing results you may find.

    Best,

    Andy Robles

  • 0 in reply to SOURABH JAIN
    TI__Genius 13760 points

    Hi,

    Thank you for your patience and sharing the information. Looking at the layout I don't see a clear issue that would cause this problem.

    One thing I would like to circle back to is the fact that in one of the waveforms you shared the DESAT pin of the HIGH side driver is not actually reaching the 9V DESAT threshold that would trigger short circuit protection. I am wondering if during the short circuit event the test setup is creating radiated noise that is affecting the short circuit detection circuits. Is there a way you could rerun the high side short circuit test by shielding the gate driver from potential high current power stage components/traces in the system?

    Please do share any other information you've captured since the last post.

    Best regards,

    Andy Robles

  • 0 in reply to Andy Robles
    Prodigy 40 points

    Dear Andy,

    Thank you for being so concerned 

    We have taken a few more results. also, add two diodes connected to the switch collector pin. Precise 47pf cap is connected across Cblk. We are rectifying probing mistakes and taking these results.

    you clearly see DESAT rise above the threshold limit and Fault detected eventually pulses are off.

    Now if you find anything else in waveform please let me know.

  • 0 in reply to SOURABH JAIN
    TI__Genius 13760 points

    Hi,

    The waveforms look a lot better and clearly show the gate driver short circuit protection is being triggered. As mentioned before there are some slight differences between the performance of high side and low side driver due to board design(gate driver and power stage), and power stage transients. For this reason running this type of tests is important to understand exactly how the short circuit mechanism reacts with your specific system/design in order to fine tune to meet your requirements.

    Could you provide more details on the concern or are there any additional questions for UCC21750?

    Best regards,

    Andy Robles