TPS652190CRHBR the tolerance of the soft error of the internal memory

Hi Hasegawa Hiroaki,

Here is an FAQ on soft error rate (SER). From the FAQ, "We generally do not test products but designed test chips containing production SRAM arrays and sequential logic arrays to enable accurate modeling of SER."

I have found this thread on how to gain access to our SER calculator. I am reaching out to another TI employee to see how we can get you access. I will update you when they reply to me.

Kind regards,

Conner Gillette

The employee I reached out to on the 25th has not responded. I have tried reaching out to another TI employee for assistance. My apologies for the delay.

Kind regards,

Conner Gillette

I should have access in a few hours and will update you then.

Regards,

Conner

Hi Hiroaki-san,

Unfortunately our apps team is not familiar with this simulator tool and Conner was not able to make any progress. From this other thread, it looks like there may be a way to put in a request to a different team, but I am not sure if this still applies:

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/731851/soft-error-rate-estimator-calculator

Best regards,

Matt