UCC21750: Application Issues

Hi Francis,

Find comments for the questions below:

Francis Jiang said:

Consistency test report(Monte Carlo), including propagation delay, driver rise/fall time, current sharing application(2pcs UCC21750 driver paralleled 2 SiC MOS)

The min and max specification provided in the datasheet account for Monte Carlo simulations, and real silicon data. The customer should use these values in their evaluation of the use of UCC21750 in their application. Additionally, I would like to comment that driving parallel MOSFETs with each MOSFET being driven by their own gate driver is not a typical application and not typically seen in the market. Getting these timings down accounting for process and temperature variation of not just the gate driver, but the whole system would be extremely difficult. Design usually use the same gate driver to drive the parallel MOSFETs. If the customer needs a gate driver with higher output current they can use an external BJT buffer to drive both MOSFETs. This would save them the need of getting an additional gate driver and complexity of the design. An example can be found in Figure 9-3 of the UCC21750-Q1 datasheet as shown below:

Francis Jiang said:

Whether this device's out is voltage source or current source? Will it source/sink current change when Vg changing?

The gate driver is a voltage source which peak current is determined by the internal pull up and pull down MOSFETs.

Francis Jiang said:

Internal value of Rnmos, Rol, Roh.

UCC21750 has a hybrid up structure that uses a PMOS in parallel with an NMOS for pull up and an NMOS for pull down. The values can be found in the datasheet. ROH = PMOS, ROL = NMOS (pull up NMOS in parallel with the PMOS has the same resistance)

Francis Jiang said:

Whether the Rdson of Miller Clamp will change when the clamp current changing? For example, 2A clamp current and 6A clamp current. From my understanding, the clamp current cannot reach 6A, right?

The RDSON does not change. Customer must consider the negative voltage bias and the expected amount of current based on the MOSFET gate to drain capacitance and expected power stage dV/dt. The current sink through the gate driver miller clamp would be I = C (dV/dt). If that current multiplied by the ON resistance of the MOSFET exceeds 2V the voltage on the gate would rise above VEE + 2V which would disable the miller clap and potentially cause the MOSFET to turn on. Customer should ensure to maintain the current low enough to not reach VEE + 2V on the gate due to the miller current injection. This is done by choosing a MOSFET with small gate to drain capacitance, and limiting the dV/dt by slowing down the switching transient with higher gate resistors.

Best regards,

Andy Robles