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BQ76952: Bits Setting in Alarm Status Register and Alarm Raw Status, How Exactly they Work?

Part Number: BQ76952

Hi,

I think, I'm missing something in understanding the bits setting in Alarm Status and Alarm Raw Status registers.

My assumption is whenever an alert or fault is triggered in Safety Alert A/B/C or Safety Status A/B/C registers causes to set the bit in Alarm Raw Status as well as in Alarm Status registers, provided they are enabled in Enabled Protections A/B/C and in SF Alert Mask A/B/C. I'm reading Alarm Status register for every 10 msec and checking for MSK_SFALERT, SSBC and SSA. If they set then clearing those bits by writing '1' to corresponding bit in Alarm Status register and reading Safety Alert A/B/C or Safety Status A/B/C to know which causes the alert or fault.

As per my understanding bits MSK_SFALERT, SSBC or SSA in Alarm Status register should be set as long as alert or fault remain triggerred. But my observation is If I clear these bits by writing '1', they are not setting again in Alarm Status register.

Please help me in understanding how exactly they work? Or Am I missing anything?

Thanks,

Satheesh

  • Hello Satheesh,

    Your understanding is correct. Once you write '1' to the respective bits, it will clear. This would not re-set the bit again, unless the protection were to occur again.

    Best Regards,

    Luis Hernandez Salomon

  • Thank you Luis for quick reply,

    In that case, how do I track alert. An alert can be converted into fault after delay and alert bit in Safety Alert A/B/C becomes '0'.

    Do I need to poll Alarm Raw Status? If I need to poll Alarm Raw Status, I can use Alarm Raw Status only instead Alarm Status to get alert or fault. So, Alarm Status(In case Alerts & Faults) can be useful in case of interrupts only.

    If I'm using polling method I need to read Alarm Raw Status to get alerts & faults. Am I correct?

  • Hello Satheesh,

    The ALERT functionality can be configured to both, trigger an alert when an fault alert (Fault condition present but protection not triggered) and fault status (Fault condition caused protection to trigger). So the ALERT would trigger at different points in both cases. So once the ALERT pin triggers an interrupt for your MCU, the MCU can check what caused the ALERT to trigger and make a decision.

    Hope that helped clarify things Slight smile

    Best Regards,

    Luis Hernandez Salomon

  • Thank you Luis,

    I understand this, but my question is if I use polling instead interrupt for alert, how do I track alert which can be only an alert not turned into fault. That means when an alert triggered let say COV, but before triggering a fault the COV condition disappers. So there is no chance to trigger COV fault. To track only alert I need to read Alarm Raw Status correct?

  • Hello Satheesh,

    As I said, the ALERT can be configured to trigger if an OV condition (without triggering the fault) is present. 

    Safety Alerts indicate that a fault-leading condition is present, but it does not indicate a fault has triggered.

    Safety Status indicate that a fault has actually triggered.

    The alert functionality can be configured to latch for either or both of these conditions, so your MCU can distinguish if a fault condition was present (even if the fault did not trigger, this would be the example you gave of "alert triggered let say COV, but before triggering a fault the COV condition disappers")

    I'd advise to read Section 6.6 ALERT Pin Operation of the TRM.

    Best Regards,

    Luis Hernandez Salomon