Hi,
I think, I'm missing something in understanding the bits setting in Alarm Status and Alarm Raw Status registers.
My assumption is whenever an alert or fault is triggered in Safety Alert A/B/C or Safety Status A/B/C registers causes to set the bit in Alarm Raw Status as well as in Alarm Status registers, provided they are enabled in Enabled Protections A/B/C and in SF Alert Mask A/B/C. I'm reading Alarm Status register for every 10 msec and checking for MSK_SFALERT, SSBC and SSA. If they set then clearing those bits by writing '1' to corresponding bit in Alarm Status register and reading Safety Alert A/B/C or Safety Status A/B/C to know which causes the alert or fault.
As per my understanding bits MSK_SFALERT, SSBC or SSA in Alarm Status register should be set as long as alert or fault remain triggerred. But my observation is If I clear these bits by writing '1', they are not setting again in Alarm Status register.
Please help me in understanding how exactly they work? Or Am I missing anything?
Thanks,
Satheesh