TPS3823: RESET latches to logic low state

Hi Aruna,

What is the current VDD voltage when the device goes on the latch state?

Jesse 

Hi,

Can you reply for the same

Hi Aruna,

Are you able to provide the schematic that your are using? For this device there are only two states that can latch the RESET 1.) Vdd < Vit- and 2.) MR  < VIL(max).

Jesse 

Hi Jesse,

PFA Schematic.

Hi Jesse,

I am testing my product with this circuit from 5days and same issue is recurring(reset latched to low after some time). 

The following are the wave for the same.

Here,

Channel 1 indicates WDI pulse from controller

Channel 2 indicates VDD

Channel 3 indicates Reset

Channel 4 indicates MR 

Why reset latched in A version also. Please could share information ASAP. 

Hi Aruna, 

Why is MR only showing 2V? I see that your VDD and MR is connected to the same rail. Are you probing VDD on a test-point or on the device VDD?

Jesse 

Hi Jesse,

Yes, MR and VDD connected on same rail. I probed on Device not at test point.

Hi Aruna,

I will have to consult with our design team, I will give you an update Monday, 2/12

Jesse