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TPS25750: Questions about how to implement PBMs and write patch bundle.

Christopher John
Prodigy 10 points
Part Number: TPS25750
Other Parts Discussed in Thread: TPS65982

I'm trying to write a patch bundle to the TPS25750 using the PBMs function. I have a few questions regarding implementation and also side effects.

When looking at the data payload description for this command I can see that it takes a four byte size. If my bundle were 24,000 bytes, would the order be Device Addr. -> Len (6) -> 0x00 -> 0x00 -> 0x5D -> 0xC0 -> Slave Addr. -> Timeout?

I understand the the slave address is a user specified address, but to be clear this address refers to itself (the TPS25750)? And it can be anything other than 0x00 and the defined ADCINx addresses, correct?

When sending the patch bundle to the I2C slave address mentioned above, should the data be sent raw (Slave Addr. -> data bytes), or should I be including a length before the data as well  (Slave Addr. -> Length of patch segment -> data bytes)? Adding a byte diagram for this in the documentation would be very useful, unless I'm overlooking something that should be obvious.

Would looping, say 128 bytes of this raw data, until I'm finished be a reasonable way to accomplish this? (Slave Addr. -> data byte 1 -> data byte n -> data byte 128)

Can I write the entire 32k bin file that is intended for the EEPROM for this PBMs command, or is there anything extra I have to include/filter out? Presumably the 32k EEPROM file contains both high and low region patch bundle.



And finally, as a side effect does the patch also get written to the EEPROM? My guess is not.

  • +1
    TI__Mastermind 34200 points

    Hi,

    PBMx is not a process designed for writing binary to EEPROM, it directly writes to device's SRAM.

    When you are performing PBMx you do not need to write the full flash binary generated from the GUI as that is meant for EEPROM as there are two region in full flash binary for the 2 region of memory in EEPROM. You will want to write the low region binary in PBMx since you are directly writing to TPS25750's SRAM. Low region binary will usually be around half of the file size of full flash binary.

    Here is a power point on PBMx process and the I2C log for PBMx (please be aware there two devices being updated via PBMx in the log so you see address 0x20 and 0x21). The flow chart and I2C log of the full process should give you a better understand of this process.

    2543.PBMx.pptxPBMx_PowerUp_Two_994.xlsx

    Christopher John said:
    I understand the the slave address is a user specified address, but to be clear this address refers to itself? And it can be anything other than 0x00 and the defined ADCINx addresses, correct?

    Think of this address as a communication channel instead. You choose an address that will not be use in the system to send the patch bundle to PD. Once the process is done we no longer interact with that channel.

    Christopher John said:
    Would looping, say 128 bytes of this raw data, until I'm finished be a reasonable way to accomplish this?

    I would recommend to do 64 bytes write each cycle just like in the I2C log.

    Regards

  • 0 in reply to Tommy Lin
    Prodigy 10 points

    Fantastic info. Thanks a lot! I think briefly mentioning how the patch data is sent after the PBMs command would be useful in the official documentation, despite it being a simple write operation.

    Is there any particular rational for 64 bytes? And (more importantly for me) is there a diagram or chart I can reference to see how the data is organized in the bin file output by the program so I can cut out the data I need to send?

  • 0 in reply to Christopher John
    TI__Mastermind 34200 points

    Hi,

    You will need to write the whole low region binary output since it contains necessary information for the device to boot from SRAM.

    For security purposes we do not reveal how the data in organized in the full flash or low region binary.

    Regards

  • 0 in reply to Tommy Lin
    Prodigy 10 points

    Perhaps my question was improperly worded. So you cannot tell me where exactly the low region exists within the full flash? I'm attempting to write (from a single file) the low region to the unit and then write the full flash to EEPROM once the unit is in APP mode. I basically need to cut the low region data out of the full flash. I don't need to know the exact details of what the low region data is, just where its located in the full flash.

    I found this document on another question. https://www.ti.com/lit/an/slva783a/slva783a.pdf
    Is the chart found in 3.1 what I'm asking for, or is the full flash different for the TPS25750?

  • 0 in reply to Christopher John
    TI__Mastermind 34200 points

    Hi,

    Yes the full flash structure for TPS65982 is different from TPS25750.

    You don't need to and cannot cut out the low region data out of the full flash because there are information in the header that needs to be checked when loading it to device. Cutting out the low region out of the full flash then write to device will just cause failure.

    If you are trying to do PBMx you can only use the low region binary (in C array format if you are using EC to write it via I2C).

    Regards